1. Aum Amriteswaryai Namah:

2. SUB ROUTINES Instead of repeating same program segments at all locations, they are written and stored separately; Each such block of instructions which carries out a specific and well defined task is called a ‘Subroutine’.

3. Halt the main program Provide returning to the same point. Transfer control to the subroutine. Execute the subroutine. Revert to the main routine.

4. MOVWF CALL bb aa-2 aa-1 aa aa+1 aa+2 bb-1 bb bb+1 cc-1 cc cc+1 RETURN Main Routine Sub Routine 2 3 aa+1 1 4 Program Memory PC Content Subroutine operations

5. Stack contents should remain undisturbed during the execution of the subroutine. Registers used in the main pgm and those in the subroutine are not to be mixed up. While using Goto statement, ensure that program control is brought back to the subroutine ( using RETURN) CALL statement has to specify the subroutine address;13 bits PC is generated with 11 bits of address and PCLATH<4:3> as MS bits.

6. SUB ROUTINE NESTING  Calling of one subroutine inside another

7. Sequence of operation during Subroutine nesting….

8. Regular operation of the processor is interrupted and a priority activity is carried out; once the same is completed, the regular operation is resumed

9. Increment PC Fetch & execute next instruction Interrupt Flag Save return address in stack Attend to Interrupt (Carry out ISR) Retrieve return address from Stack reset set Processor Operation while interrupted

10. CC all occurs at specific and predetermined locations in the main routine. CC an ask for service without any prior notice. HH ardware initiated. SS oftware initiated. RR equest can come expectedly. RR equest can come unexpectedly; may have to carry out some emergency activities-like saving the status of scratch pad registers.

11. Any of the peripherals associated with PIC can interrupt the microcontroller. External Peripherals can also interrupt the processor. Each interrupt has an associated Interrupt Flag. Interrupt can be masked by resetting its Interrupt Enable Flag. Three conditions are to be satisfied for a source to interrupt The interrupt flag has to be set by the Interrupt Request(IRQ) going high. The interrupt has to be enabled by the microcontroller by setting the concerned Interrupt Enable Flag. The GIE flag has to be set-again by the controller.

12. PIC 16F877A has 10 sources of interrupt: External Interrupt TMR0 Over Flow Interrupt PORT B Change Interrupt Comparator Interrupt USART Interrupt TX USART Interrupt RX CCP Interrupt TMR1 Over Flow Interrupt TMR2 Match Interrupt Data EEPROM Interrupt

13. INTERBIET0IFINTFT0IEGIEPEIERBIF B4B3B2B1B5B7B6B0 INTCON REGISTER GIE  GLOBAL INTERRUPT ENABLE BIT PIE  PERIPHERAL INTERRUPT ENABLE BIT T0IE  TMER 0 OVERFLOW INT ENABLE BIT INTE  RB0/INT EXT INT ENABLE BIT RBIE  RB PORT CHANGE INT ENABLE BIT T0IF  TMR0 OVERFLOW INT FLAG BIT INTF  RB0/INT EXT INT FLAG BIT RBIF  RB PORT CHANGE INT FLAG BIT

14. TMR1IE TMR1IF TMR2IE TMR2IF CCPIE CCPIF CMIE CMIF TXIE TXIF RXIE RXIF EEIE EEIF TMR0IE TMR0IF INTF INTE RBIF RBIE PEIE GIE INT

15. INTERRUPT LOGIC

16. Interrupt Request and Response – Sequence of Activities

17. Positioning of ISR in Program Memory TT he PIC has the provision to start the ISR at location 0X004H TT he location 0X04H can have a simple GOTO ISR instruction.

18. 0x04h Interrupt from source A Service routine A Service routine B yes no 004h BTFSS PIR,A GOTO SRB --------------- --[ISR A]---- ---------------- RETFIE SRB : ---[ISR B]--- ------------- RETFIE

19. Stores the W register Stores the Status register Executes the ISR code Restores the Status Restores the W register TT he common memory area with addresses 70h to 7Fh can be used to store such data. It eliminates the need to switch banks back and forth to access data during interrupt service.

20. Scratchpad register assignment and status saving for each service routine have to be done with care to avoid any mix up. While using Goto statement, ensure that program control is brought back to the subroutine (using RETFIE) The return addresses of subroutines as well as those of interrupt services are saved in the same stack. The service routine can complete the more prioritized task of one source, enable GIE(to allow IRQ from source B) and then take up the second (non priority)task. If more interrupts which exceeds the 8 level stack, are involved; assign a different processor.