1. Rabel Talpur:12BME#025

2.  40-pin chip  Developed by Motorola in 1975  16 address lines and 8 data lines  Used only +5V

3.  Registers  Arithmetic and Logic Unit  Control Unit  Program Counter  Stack Pointer  Status Flags

4. A B IX PC SP CC Accumulator A Accumulator B Index register X Program counter Stack pointer Condition code register

5.  The micro processor unit contains 2 accumulators designed ACCA and ACCB.  Each accumulators is 8 bits (one byte) long and is used to hold operands and data from the arithmetic logic unit

6.  The index register (x) is a 16 bit (2 byte) register which is primarily used to store a memory address in the indexed mode of memory addressing.  The index register may be decremented, incremented and stored.

7.  The condition code register is an 8 bit register. each individual bit may get set or cleared from of an instruction.  Each instruction effects the condition code register differently.  The primary use of this register is execution of the conditional branch instruction.

8.  ALU is a digital circuit that performs integer arithmetic and logical operations.  It is fundamental building block of central processing unit.

9.  It is a component of central processing unit which direct the operation of processor.  It control communication and co-ordination between i/o devices.  It reads interrupts instructions and determine the sequence for processing the data.  It performs the task of fetching, decoding, managing, execution and finally storing results.

10.  Program counter contain the address of the memory containing the next instruction to be executed.  It is incremented automatically after each instruction  In 6800, it is a 16 bits register

11.  Used to point to the memory location where all registers will be saved when an interrupt occurs  It is a 16 bit register, contain an address of a memory

12.  16 address wires =it can address 2 16 memory locations  It is an 8 bit microprocessor => 8 data bits  Speed up to 4 MHZ  Architecture

13. S.No 6800 8085 1It has two accumulators Only one accumulator is present 2Uses frequency 1 MHzuses frequency from 3 to 5 MHz 3It has index registerNo index register is present 4Has 3 interrupts (IRQ,NMI,SWI) Has five interrupts (Trap, RST 7.5,RST 6.5, RST 7.5, INTR)

14. BLOCK DIAGRAM OF 6800

16.  INTERRUPTS  IRO  mask able interrupt. When the interrupt occurs the program counter, index register, accumulators and condition code registers are stored in the stack, the further interrupts are disabled and the processor jumps to memory location address of which is stored in memory FFF8h - FFF9h. To return from the interrupt the processing routine should use RTI instruction. This interrupt can be enabled/disabled using CLI/SEI instructions. INTERRUPTS IRQ

17.  NMI non-maskable interrupt. When the interrupt occurs the program counter, index register, accumulators and condition code registers are stored in the stack, the further interrupts are disabled and the processor jumps to memory location address of which is stored in memory FFFCh - FFFDh. To return from the interrupt the processing routine should use RTI instruction. This interrupt can not be disabled. NMI

18.  SWI  software interrupt. This interrupt can be only invoked from the program. When the interrupt occurs the processor stores the program counter, index register, accumulators and condition code registers in the stack, disables the further interrupts and jumps to memory location address of which is stored in memory FFFAh - FFFBh. To return from the interrupt the processing routine should use RTI instruction. This interrupt can not be disabled. SWI

19.  None.  Accumulator A (ACCA) is an 8-bit register used for arithmetic and logic operations.  Accumulator B (ACCB) is an 8-bit register used for arithmetic and logic operations. I/O ports REGISTERS

20.  Index (IX) is a 16-bit register usually used for temporary storage or as an index when indexed addressing is used.  Program counter (PC) is a 16-bit register.  Stack pointer (SP) is a 16-bit register.

21.  Condition code register contains the following flags:  Half carry (H) - set if there was a carry from bit 3 to bit 4 of the result when the result was calculated.  Interrupt mask (I) - set if the IRQ interrupt is disabled.  Negative (N) - set if the most significant bit of the result is set.  Zero (Z) - set if the result is zero.  Overflow (V) - set if there was an overflow during last result calculation.  Carry (C) - set if there was a carry from the bit 7 during last result calculation. Condition code register contains the following flags:

22.  Instruction Set  6800 instruction set consists of 72 instructions:  Data moving instructions.  Arithmetic - add, subtract, negate, increment, decrement and compare.  Logic - AND, OR, exclusive OR, complement and shift/rotate.  Control transfer - conditional, unconditional, call subroutine and return from subroutine.  Other - clear/set condition flags, bit test, stack operations, software interrupt, etc.

23.  Addressing modes  Implied - the data value/data address is implicitly associated with the instruction.  Accumulator - the instruction implies that the data is one of the accumulator registers.  Immediate - 8-bit or 16-bit data is provided in the instruction.

24.  MEMORY  Program, size is 64 KB. data and stack memories occupy the same memory space. The total addressable memory.  DATA MEMORY  data can be anywhere in memory space. MEMORY DATA MEMORY

25.  program can be located anywhere in memory. Jump and subroutine call instructions can be used to jump anywhere in memory. PROGRAM MEMORY

26.  STACK MEMORY  stack can be placed anywhere in memory space.  FFF8h - FFF9h: Pointer to IRQ interrupt- processing routine.  FFFAh - FFFBh: Pointer to software interrupt- processing routine. STACK MEMORY RESERVED MEMORY LOCATION

27.  FFFCh - FFFDh: Pointer to NMI interrupt- processing routine.  FFFEh - FFFFh: Pointer to RESET handling code.  Some memory addresses may be reserved for memory mapped I/O as the processor doesn't have hardware I/O capability.

28. INSTRUCTION SET MOTOROLA 6800 PRESENTED BY: MURK SALEEM 12BME19

29.  Group of instructions executed by microprocessor is called as: “ INSTRUCTION SET ”.  Motorola-6800 has 72 instructions.

30. 1.ARITHMETIC INSTRUCTIONS

31. OPERATIONOPCODE/ MNEMONICS ALL REGISTER LABELS REFER TO CONTENTS 1.AdditionADDAA+M  A ADDBB+M  B 2.Add Accumulators ABAA+B  A 3.Add With CarryADCAA+M+C  4.Compliment 2`s (Negative) NEG00-M  M NEG A00-A  A NEG B00-B  B 5.SubtractSUB AA-M  A SUB BB-M  B 6.Subtract Accumulators SB AA-B  A Two`s compliment arithmetic is used in “MP6800” which allow us to take the 2’s compliment of a number. The negative instruction allows us to operate on a byte in memory without first fetching the operand from memory. In the past, we have loaded the operand, performed operation and then stored the new operand

32. 2. DATA HANDLING INSTRUCTIONS:

33. OPERATIONOPCODES/ NMEMONICS ALL REGISTER LABELS REFER TO CONTENTS 1.ClearCLR00  M CLR A00  A CLR B00  B 2.DecrementDECM-1  M DEC AA-1  A DEC BB-1  B 3.IncrementINCM+1  M INC AA+1  A INC BB+1  B 4.Load Accumulator LDAAMAMA LDABMBMB 5.Rotate LeftROLM ROL AA ROL BB “CLEAR” instruction allows us to clear a memory or either accumulator. In the past, we have cleared bytes of first clearing the accumulator then storing the result in the proper memory location. However, the CLR instruction allows us to clear a memory location with a single instruction.

34. OPERATIONOPCODES/ NMEMONICS ALL REGISTER LABELS REFER TO CONTENTS 6.Rotate RightRORM ROR AA ROR BB 7.Store Accumulator STA AAMAM STA BBMBM 8. Transfer Accumulator TABABAB TBABABA “TRANSFER ACCUMULATOR” copies the contents of accumulator A or B. After this instruction is executed, the number originally present in any accumulator(eg: A) will be in both accumulators.

35. 3. LOGIC INSTRUCTIONS:

36. OPERATIONOPCODES/ NMEMONICS ALL REGISTER LABELS REFER TO CONTENTS 1. AndAND AA.M  A AND BB.M  B 2.Compliment,1`sCOM M  M COM A A  A 3.X-OREOR AA (+) M EOR BB (+) M 4.OROR AA+M  A OR BB+M  B

37. 4. DATA TEST INSTRUCTIONS:

38. OPERATIONOPCODES/ NMEMONICSALL REGISTER LABELS REFER TO CONTENTS 1. Bit TestBIT AA.M BIT BB.M 2.CompareCMP AA—M CMP BB—M 3.Compare AccumulatorsCBAA—B “BIT TEST” this instruction is very similar to the AND instructions. In both cases, the contents of the specified accumulator are ANDed with the contents of the selected memory location. The difference is that with the bit test instruction no logical product is produced. Neither the contents of the accumulator nor memory are altered in any way. However condition code are affected just as if the AND operation had taken place. Consider BITA instruction, when executed, A is ANDed with M. If result is 0000, the Z register is set. Otherwise, the Z register is cleared.

39. 5. INDEX REGISTER AND STACK POINTER INSTRUCTIONS: The index and stack pointer are 16-bit registers. That allow us to control the operation of these registers. Because of the 16-bit format, the load, store, and compare instructions are slightly different.

40. OPERATIONOPRANDS/ NMEMONICS ALL REGISTER LABELS REFER TO CONTENTS 1.Compare Index Reg.CPX 2.Decrement Index RegisterDEXX-1  X 3.Decrement Stack PointerDESSP-1  SP 4. Increment Stack PointerINSSP+1  SP 5.Increment Index RegisterINXX+1  X

41. 6.BRANCH INSTRUCTIONS: Condition code register contains the following flags: Half carry (H) - set if there was a carry from bit 3 to bit 4 of the result when the result was calculated. Interrupt mask (I) - set if the IRQ interrupt is disabled. Negative (N) - set if the most significant bit of the result is set. Zero (Z) - set if the result is zero. Overflow (V) - set if there was an overflow during last result calculation. Carry (C) - set if there was a carry from the bit 7 during last result calculation. Condition code register contains the following flags: Half carry (H) - set if there was a carry from bit 3 to bit 4 of the result when the result was calculated. Interrupt mask (I) - set if the IRQ interrupt is disabled. Negative (N) - set if the most significant bit of the result is set. Zero (Z) - set if the result is zero. Overflow (V) - set if there was an overflow during last result calculation. Carry (C) - set if there was a carry from the bit 7 during last result calculation.

42. OPERATIONOPCODE/ NMEMONICS ALL REGISTER LABELS REFER TO CONTENTS 1.Branch AlwaysBRANONE 2.Branch If ClearBCCC=0 3.Branch If Carry SetBCSC=1 4.Branch If MinusBMIN=1 5.Branch If PlusBPLN=0 6.Branch If Over-Flow SetBVSV=1 7.Branch If Over-Flow Clear BVCV=0

43. 7. CONDITION CODE REGISTER:- The 6800 uses these instructions in order to direct access the condition codes.

44. OPERATIONOPCODES/ NMEMONICSALL REGISTER LABELS REFER TO CONTENTS 1.Clear CarryCLC0C0C 2.Clear Interrupt MaskCLI0I0I 3.Clear Over-FlowCLV0V0V 4.Set CarrySEC1C1C 5.Set Interrupt MaskSEI1I1I 6.Set Over-FlowSEV1V1V