1. Computer Systems Overview

2. Page 2 W. Stallings: Operating Systems: Internals and Design, ©2001 Operating System Exploits the hardware resources of one or more processors Provides a set of services to system users Manages secondary memory and I/O devices

3. Page 3 W. Stallings: Operating Systems: Internals and Design, ©2001 Basic Elements Processor Main Memory volatile referred to as real memory or primary memory I/O modules secondary memory devices communications equipment terminals System bus communication among processors, memory, and I/O modules

4. Page 4 W. Stallings: Operating Systems: Internals and Design, ©2001 Processor Two internal registers Memory address register (MAR)  Specifies the address for the next read or write Memory buffer register (MBR)  Contains data written into memory or receives data read from memory I/O address register I/O buffer register

5. Page 5 W. Stallings: Operating Systems: Internals and Design, ©2001 Top-Level Components

6. Page 6 W. Stallings: Operating Systems: Internals and Design, ©2001 Processor Registers User-visible registers Enable programmer to minimize main-memory references by optimizing register use Control and status registers Used by processor to control operation of the processor Used by privileged operating-system routines to control the execution of programs

7. Page 7 W. Stallings: Operating Systems: Internals and Design, ©2001 User-Visible Registers May be referenced by machine language Available to all programs - application programs and system programs Types of registers Data Address  Index  Segment pointer  Stack pointer

8. Page 8 W. Stallings: Operating Systems: Internals and Design, ©2001 User-Visible Registers Address Registers Index  Involves adding an index to a base value to get an address Segment pointer  When memory is divided into segments, memory is referenced by a segment and an offset Stack pointer  Points to top of stack

9. Page 9 W. Stallings: Operating Systems: Internals and Design, ©2001 Control and Status Registers Program Counter (PC) Contains the address of an instruction to be fetched Instruction Register (IR) Contains the instruction most recently fetched Program Status Word (PSW) Condition codes Interrupt enable/disable Supervisor/user mode

10. Page 10 W. Stallings: Operating Systems: Internals and Design, ©2001 Control and Status Registers Condition Codes or Flags Bits set by the processor hardware as a result of operations Examples  Positive result  Negative result  Zero  Overflow

11. Page 11 W. Stallings: Operating Systems: Internals and Design, ©2001 Instruction Execution Two steps Processor reads instructions from memory  Fetches Processor executes each instruction

12. Page 12 W. Stallings: Operating Systems: Internals and Design, ©2001 Instruction Cycle

13. Page 13 W. Stallings: Operating Systems: Internals and Design, ©2001 Instruction Fetch and Execute The processor fetches the instruction from memory Program counter (PC) holds address of the instruction to be fetched next Program counter is incremented after each fetch

14. Page 14 W. Stallings: Operating Systems: Internals and Design, ©2001 Instruction Register Fetched instruction is placed in the instruction register Categories Processor-memory  Transfer data between processor and memory Processor-I/O  Data transferred to or from a peripheral device Data processing  Arithmetic or logic operation on data Control  Alter sequence of execution

15. Page 15 W. Stallings: Operating Systems: Internals and Design, ©2001 Characteristics of a Hypothetical Machine

16. Page 16 W. Stallings: Operating Systems: Internals and Design, ©2001 Example of Program Execution

17. Page 17 W. Stallings: Operating Systems: Internals and Design, ©2001 Direct Memory Access (DMA) I/O exchanges occur directly with memory Processor grants I/O module authority to read from or write to memory Relieves the processor responsibility for the exchange

18. Page 18 W. Stallings: Operating Systems: Internals and Design, ©2001 Interrupts Interrupt the normal sequencing of the processor Most I/O devices are slower than the processor Processor must pause to wait for device

19. Page 19 W. Stallings: Operating Systems: Internals and Design, ©2001 Classes of Interrupts

20. Page 20 W. Stallings: Operating Systems: Internals and Design, ©2001 Program Flow of Control Without Interrupts

21. Page 21 W. Stallings: Operating Systems: Internals and Design, ©2001 Program Flow of Control With Interrupts, Short I/O Wait

22. Page 22 W. Stallings: Operating Systems: Internals and Design, ©2001 Program Flow of Control With Interrupts; Long I/O Wait

23. Page 23 W. Stallings: Operating Systems: Internals and Design, ©2001 Interrupt Handler Program to service a particular I/O device Generally part of the operating system

24. Page 24 W. Stallings: Operating Systems: Internals and Design, ©2001 Interrupts Suspends the normal sequence of execution

25. Page 25 W. Stallings: Operating Systems: Internals and Design, ©2001 Interrupt Cycle

26. Page 26 W. Stallings: Operating Systems: Internals and Design, ©2001 Interrupt Cycle Processor checks for interrupts If no interrupts fetch the next instruction for the current program If an interrupt is pending, suspend execution of the current program, and execute the interrupt-handler routine

27. Page 27 W. Stallings: Operating Systems: Internals and Design, ©2001 Timing Diagram Based on Short I/O Wait

28. Page 28 W. Stallings: Operating Systems: Internals and Design, ©2001 Timing Diagram Based on Short I/O Wait

29. Page 29 W. Stallings: Operating Systems: Internals and Design, ©2001 Simple Interrupt Processing

30. Page 30 W. Stallings: Operating Systems: Internals and Design, ©2001 Changes in Memory and Registers for an Interrupt

31. Page 31 W. Stallings: Operating Systems: Internals and Design, ©2001 Changes in Memory and Registers for an Interrupt

32. Page 32 W. Stallings: Operating Systems: Internals and Design, ©2001 Multiple Interrupts Disable interrupts while an interrupt is being processed

33. Page 33 W. Stallings: Operating Systems: Internals and Design, ©2001 Multiple Nested Interrupts Define priorities for interrupts

34. Page 34 W. Stallings: Operating Systems: Internals and Design, ©2001 Multiple Interrupts

35. Page 35 W. Stallings: Operating Systems: Internals and Design, ©2001 Multiprogramming Processor has more than one program to execute The sequence the programs are executed depend on their relative priority and whether they are waiting for I/O After an interrupt handler completes, control may not return to the program that was executing at the time of the interrupt

36. Page 36 W. Stallings: Operating Systems: Internals and Design, ©2001 Memory Hierarchy Faster access time, greater cost per bit Greater capacity, smaller cost per bit Greater capacity, slower access speed

37. Page 37 W. Stallings: Operating Systems: Internals and Design, ©2001 Going Down the Hierarchy Decreasing cost per bit Increasing capacity Increasing access time Decreasing frequency of access of the memory by the processor Locality of reference

38. Page 38 W. Stallings: Operating Systems: Internals and Design, ©2001 Secondary Memory Nonvolatile Auxiliary memory Used to store program and data files

39. Page 39 W. Stallings: Operating Systems: Internals and Design, ©2001 Disk Cache A portion of main memory used as a buffer to temporarily to hold data for the disk Disk writes are clustered Some data written out may be referenced again. The data are retrieved rapidly from the software cache instead of slowly from disk

40. Page 40 W. Stallings: Operating Systems: Internals and Design, ©2001 Cache Memory Invisible to operating system Increase the speed of memory Processor speed is faster than memory speed Exploit the principle of locality

41. Page 41 W. Stallings: Operating Systems: Internals and Design, ©2001 Cache Memory

42. Page 42 W. Stallings: Operating Systems: Internals and Design, ©2001 Cache Memory Contains a copy of a portion of main memory Processor first checks cache If not found in cache, the block of memory containing the needed information is moved to the cache and delivered to the processor

43. Page 43 W. Stallings: Operating Systems: Internals and Design, ©2001 Cache/Main Memory System

44. Page 44 W. Stallings: Operating Systems: Internals and Design, ©2001 Cache Read Operation

45. Page 45 W. Stallings: Operating Systems: Internals and Design, ©2001 Cache Design Cache size Small caches have a significant impact on performance Block size The unit of data exchanged between cache and main memory Larger block size more hits until probability of using newly fetched data becomes less than the probability of reusing data that have to be moved out of cache

46. Page 46 W. Stallings: Operating Systems: Internals and Design, ©2001 Cache Design Mapping function Determines which cache location the block will occupy Replacement algorithm Determines which block to replace Least-Recently-Used (LRU) algorithm

47. Page 47 W. Stallings: Operating Systems: Internals and Design, ©2001 Cache Design Write policy When the memory write operation takes place Can occur every time block is updated Can occur only when block is replaced  Minimizes memory write operations  Leaves main memory in an obsolete state

48. Page 48 W. Stallings: Operating Systems: Internals and Design, ©2001 Programmed I/O I/O module performs the action, not the processor Sets appropriate bits in the I/O status register No interrupts occur Processor checks status until operation is complete

49. Page 49 W. Stallings: Operating Systems: Internals and Design, ©2001 Interrupt-Driven I/O Processor is interrupted when I/O module ready to exchange data Processor saves context of program executing and begins executing interrupt-handler No needless waiting Consumes a lot of processor time because every word read or written passes through the processor

50. Page 50 W. Stallings: Operating Systems: Internals and Design, ©2001 Direct Memory Access Transfers a block of data directly to or from memory An interrupt is sent when the transfer is complete Processor continues with other work