Presentation is loading. Please wait.

Presentation is loading. Please wait.

Hewlett-Packard PA-RISC 2.0 64-Bit Processors: History, Features, and Architecture Presented By: Adam Gray Christie Kummers Joshua Madagan.

Similar presentations


Presentation on theme: "Hewlett-Packard PA-RISC 2.0 64-Bit Processors: History, Features, and Architecture Presented By: Adam Gray Christie Kummers Joshua Madagan."— Presentation transcript:

1 Hewlett-Packard PA-RISC 2.0 64-Bit Processors: History, Features, and Architecture Presented By: Adam Gray Christie Kummers Joshua Madagan

2 Computing in 64-Bit (HP & 64-bit; 32-bit or 64-bit) History of the PA-8x00 Processors (PA-8x00 family of Processors) Features and Detailed Architecture (RISC; PA-8000; PA-8700; PA-8800) HP & The Formation of the 64-Bit Chip:

3 Dawn of the 64-bit chip HP’s PA-8000 arrives in 1996 Army signs up for contract with HP Differences between the 32-bit & 64-bit Address more memory Better mathematical precision Can run 32-bit application on 64-bit system Benefits of switching to 64-bit Increased hardware / performance speed Graphics / games / sounds

4 PA-8000 Introduced: January 1996 First chip to use 64-bit PA-RISC 2.0 Architecture Contains dual floating-point and dual load/store units Has no on-chip caches Speculative execution

5 PA-8200 Introduced: May 1997 4MB SRAMs with faster access time larger cache size TLB (Translation Lookaside Buffer) and BHT (Branch History Table) were increased to reduce “wasted cycles”

6 PA-8500 Introduced: September 1998 L1 cache was integrated with the CPU die Able to handle two memory operations at the same time All data caches are 0.5 MB and are implemented as four.125 MB arrays, each with a double-word of data The instruction cache is a.5 MB four-way set associative pipeline cache with 128 bits of instruction

7 PA-8600 Introduced: January 2000 Higher clock speed Modifications to the interface bus Rework on the bus transactions A quasi LRU replacement policy for the instruction cache was added

8 PA-8700 Introduced: August 2001 Enhancements to the on-chip L1 cache and TLB A new CMOS-process helps boost the clock frequency

9 PA-8800 Introduced: October 2001 Contains two PA-8700 cores on one chip Allows core speed to run up to 1 GHz Allows for a combined 35 MB L1+L2 cache

10 Features of PA-RISC 2.0 RISC 64-Bit Computing Out-of-Order Execution Branch Prediction 4-way Superscalar Execution

11 Architecture of PA-8000

12 Architecture of PA-8700

13 Architecture of PA-8800

14 End


Download ppt "Hewlett-Packard PA-RISC 2.0 64-Bit Processors: History, Features, and Architecture Presented By: Adam Gray Christie Kummers Joshua Madagan."

Similar presentations


Ads by Google