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Fall 2006 1 EE 333 Lillevik 333f06-l20 University of Portland School of Engineering Computer Organization Lecture 20 Pipelining: “bucket brigade” MIPS.

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Presentation on theme: "Fall 2006 1 EE 333 Lillevik 333f06-l20 University of Portland School of Engineering Computer Organization Lecture 20 Pipelining: “bucket brigade” MIPS."— Presentation transcript:

1 Fall EE 333 Lillevik 333f06-l20 University of Portland School of Engineering Computer Organization Lecture 20 Pipelining: “bucket brigade” MIPS pipeline & control Pentium 4 architecture

2 Fall EE 333 Lillevik 333f06-l20 University of Portland School of Engineering Pipelining overview Pipelining –Increased performance through parallel operations –Goal: complete several operations at the same time Hazards –Conditions which inhibit parallel operations –Techniques exist to minimize the problem

3 Fall EE 333 Lillevik 333f06-l20 University of Portland School of Engineering A laundry pipeline To Do laundry: wash, dry, fold, put away Each step takes 30 minutes, but for four students.... Laundry done at 2 AM

4 Fall EE 333 Lillevik 333f06-l20 University of Portland School of Engineering Let’s speed it up (pipeline) Move one load from one step to the next But start the next load before first is complete Takes only until 9:30 PM – party time !! Bucket Brigade

5 Fall EE 333 Lillevik 333f06-l20 University of Portland School of Engineering Speedup –Ratio of serial time to parallel –Metric to compare advantages of parallel operations

6 Fall EE 333 Lillevik 333f06-l20 University of Portland School of Engineering Find the laundry speedup?

7 Fall EE 333 Lillevik 333f06-l20 University of Portland School of Engineering A computer pipeline Assume –Instructions require multiple clocks to complete –Each instruction follows approximately the same steps (stage) Method –Start initial instruction on first clock –On following clocks start subsequent instructions

8 Fall EE 333 Lillevik 333f06-l20 University of Portland School of Engineering MIPS instruction steps/stages 1.IF: Fetch instruction from memory 2.ID: Read registers while decoding instruction 3.EX: Execute the operation or calculate an address 4.MEM: Access an operand in data memory 5.WB: Write the result into a register

9 Fall EE 333 Lillevik 333f06-l20 University of Portland School of Engineering MIPS pipeline IFIDEXMEMWB IFIDEXMEMWB IFIDEXMEMWB IFIDEXMEMWB IFIDEXMEMWB  First instruction ends Fifth instruction starts 

10 Fall EE 333 Lillevik 333f06-l20 University of Portland School of Engineering Find the MIPS pipeline speedup? Assume five instructions

11 Fall EE 333 Lillevik 333f06-l20 University of Portland School of Engineering What about a large program? Series Pipelined Speedup

12 Fall EE 333 Lillevik 333f06-l20 University of Portland School of Engineering Speedup of pipeline with p stages?

13 Fall EE 333 Lillevik 333f06-l20 University of Portland School of Engineering MIPS pipelined datapath Pipeline registers added to datapath

14 Fall EE 333 Lillevik 333f06-l20 University of Portland School of Engineering Pipelined Control Signals used in later stage determined by IF/ID Save for Ex stage Save for Mem stage Save for WB stage

15 Fall EE 333 Lillevik 333f06-l20 University of Portland School of Engineering Datapath & pipelined control

16 Fall EE 333 Lillevik 333f06-l20 University of Portland School of Engineering Pentium 4 pipeline Twenty stages long Theoretical speedup of 20 Hazards ( forced sequential operations ) reduce speedup –Some instructions executed “out of order” to avoid hazard –Multiple (optimistic) pipelines created, one selected to create result, other data discarded

17 Fall EE 333 Lillevik 333f06-l20 University of Portland School of Engineering Early Pentium 4 Socket 423/ M transistors, 0.18 and 0.13 mm technology 2.0 GHz core frequency, ~60 W Integrated heat spreader, built-in thermal monitor

18 Fall EE 333 Lillevik 333f06-l20 University of Portland School of Engineering NetBurst Architecture Faster system bus Advanced transfer cache Advanced dynamic execution (execution trace cache, enhanced branch prediction) Hyper pipelined technology Rapid execution engine Enhanced floating point and multi-media (SSE2)

19 Fall EE 333 Lillevik 333f06-l20 University of Portland School of Engineering Architecture Overview

20 Fall EE 333 Lillevik 333f06-l20 University of Portland School of Engineering Front Side Bus

21 Fall EE 333 Lillevik 333f06-l20 University of Portland School of Engineering FSB Bandwidth Clocked at 100 MHz, quad “pumped” 128 B cache lines, 64-bit (8 B) accesses Split transactions, pipelined External bandwidth: 100M x 8 x 4 = 3.2 GB/s Makes better use of bus bandwidth Clock A Clock B

22 Fall EE 333 Lillevik 333f06-l20 University of Portland School of Engineering L2 Advanced Transfer Cache

23 Fall EE 333 Lillevik 333f06-l20 University of Portland School of Engineering Full-Speed L2 Cache Depth of 256 KB Eight-way set associative, 128 B line Wide instruction & data interface of 256 bits (32 B) Read latency of 7 clocks, but … Clocked at core frequency (2.0 GHz) Internal bandwidth, 32 x 2.0 G = 64 GB/s Optimizes data transfers to/from memory

24 Fall EE 333 Lillevik 333f06-l20 University of Portland School of Engineering L1 Data Cache

25 Fall EE 333 Lillevik 333f06-l20 University of Portland School of Engineering L1 Data Cache Depth of 8 KB Four-way, set associative, 64 B line Read latency of 2 clocks, but …. Dual port for one load & one store-per- clock Supports advanced pre-fetch algorithm

26 Fall EE 333 Lillevik 333f06-l20 University of Portland School of Engineering Dynamic Execution

27 Fall EE 333 Lillevik 333f06-l20 University of Portland School of Engineering Trace Cache & Branch Prediction Replaces traditional L1 instruction cache Trace cache contains ~12K decoded instructions (micro-operations), removes decode latency Improved branch prediction algorithm, eliminates 33% of P3 mis-predictions (pipeline stalls) Keeps correct instructions executing

28 Fall EE 333 Lillevik 333f06-l20 University of Portland School of Engineering Execution Engine

29 Fall EE 333 Lillevik 333f06-l20 University of Portland School of Engineering Hyper Pipelined Technology Execution pipeline contains 20 stages –Out-of-order, speculative execution unit –126 instructions “in flight” –Includes 48 load, 24 stores Rapid execution engine –2 ALUs, 2X clocked (one instruction in ½ clock) –2 AGUs, 2X clocked Results in higher throughput and reduced latency

30 Fall EE 333 Lillevik 333f06-l20 University of Portland School of Engineering Streaming SIMD Extensions FPU and MMX –128-bit format –AGU data movement register SSE2 (extends MMX and SSE) –144 new instructions –DP floating-point –Integer –Cache and memory management Performance increases across broad range of applications

31 Fall EE 333 Lillevik 333f06-l20 University of Portland School of Engineering

32 Fall EE 333 Lillevik 333f06-l20 University of Portland School of Engineering Find the laundry speedup?

33 Fall EE 333 Lillevik 333f06-l20 University of Portland School of Engineering Find the MIPS pipeline speedup? Assume five instructions

34 Fall EE 333 Lillevik 333f06-l20 University of Portland School of Engineering Speedup of pipeline with p stages? Series Parallel


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