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Presentation on theme: "Www.advancedmsinc.com EZ-COURSEWARE State-of-the-Art Teaching Tools From AMS Teaching Tomorrow’s Technology Today."— Presentation transcript:

1 EZ-COURSEWARE State-of-the-Art Teaching Tools From AMS Teaching Tomorrow’s Technology Today

2

3 80486 and Pentium

4 Microprocessor Family Microprocessor –Introduced in 1989 –High Integration On-chip 8K Code and Data cache Floating Point Unit Paged, Virtual Memory Management –168-pin PGA package –Multiprocessor Support Multiprocessor Instructions Cache Consistency Protocols

5 Internal Architecture of the Complex Reduced-Instruction-Set Computer (CRISC) RISC integer core

6 Real-Mode Software Model the same as that shown for the 80386

7 Protected-Mode Software Architecture AC: Alignment-Check flag When this bit is set, an alignment check is performed during all memory accesses at privilege level 3. If an unaligned access takes place, exception 17 occurs.

8 Control Registers AM : alignment mask -- If this is switched to 0, the alignment check is masked out. NE : Numeric Error CD : cache disable NW : not write-through WP : write protect PCD : page-level cache disable PWT : page-level write transparent

9 System-Control Instruction Set + a flush bus cycle + a write-back bus cycle

10 Page Directory and Page Table Entries

11 Hardware Architecture of the 80486

12 Signal Interfaces Pseudo-lock

13 On-Chip Cache of the 80486SX

14 Pentium Processor –32-bit Microprocessor 32-bit addressing 64-bit Data Bus –Superscalar architecture Two pipelined integer units Capable of under one clock per instruction Pipelined Floating Point Unit –Separate Code and Data Caches 8K Code, 8K Write Back Data 2-way 32-byte line size MESI cache consistency protocol –Advance Design Features Branch Prediction –237-pin PGA

15 Internal Architecture of the Pentium Processors

16 Pentium Processor Pipeline and Instruction Flow –5 stage pipeline PF : prefetch D1 : Instruction decode D2 : Address Generation EX : Execute -ALU and Cache Access WB : Write Back Intel 486Pentium I1I1 I3I3 I2I2 I4I4 I1I1 I3I3 I2I2 I4I4 I1I1 I3I3 I2I2 I4I4 I1I1 I3I3 I2I2 I4I4 I1I1 I3I3 I2I2 I4I4 PF D1 D2 EX WB I1I1 I2I2 I5I5 I6I6 I7I7 I8I8 I3I3 I4I4 I1I1 I2I2 I5I5 I6I6 I7I7 I8I8 I3I3 I4I4 I1I1 I2I2 I5I5 I6I6 I7I7 I8I8 I3I3 I4I4 I1I1 I2I2 I5I5 I6I6 I7I7 I8I8 I3I3 I4I4 I1I1 I2I2 I5I5 I6I6 I7I7 I8I8 I3I3 I4I4 PF D1 D2 EX WB

17 Pentium Processor –“U”, “V” pipes - “pairing” U : any instruction V : ‘simple instructions” as defined in the ‘Pairing” rules PF : instructions on chip cache or memory -> prefetch buffers prefetch buffers - two independent pairs of line size(32 bytes) D1 : two parallel decoders D2 : address generation for operand fetch EX : ALU operations and data cache access WB : modify processor state ; complete execution

18 Branch Prediction –Branch Target Buffer –The processor accesses the BTB with the address of the instruction in the D1 stage example) inner_loop : mov byte ptr flag[edx], al PF D1 D2 EX WB add edx, ecx PF D1 D2 EX WB cmp edx, FALSE PF D1 D2 EX WB jle inner_loop PF –486 : 6 clocks Pentium : 2 clocks with branch prediction

19 EFLAGS

20 Control Registers of the Pentium Processor

21 Enhancements to the Instruction Set

22 Hardware Architecture

23 Memory Subsystem

24 Organization of the DRAM Array

25 RAS/CAS address MUX

26 Data Bus Transceiver Circuitry

27 On-Chip Cache

28 On-chip cache operating mode

29


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