1. Designing a CPU –Reading a programs instruction from memory –Decoding the instruction –Executing the instruction –Transferring Data to/From memory / IO CPU lies at the heart of all digital computers and is responsible for:

2. A CPU is required to perform tasks by READ/WRITE operations from and to memory. For example, Area of a triangle program

3. Register transfer Language RTL RTL is not a programming language, it is a notation that describes how information is accessed from memories and registers and how it is operated on Rules: Direction is RIGHT to LEFT Square brackets [ ] indicate location For example: [D0] =MONDAY; D0 contains the value MONDAY [MAR] [PC];Copy contents of PC to MAR [3] [5];Copy contents of Location 5 to Location 3 [PC] [PC]+1;Increment PC [M(5)] [PC];Copy PC to memory address 5 [M(20)] = 6;States that memory (20) is equal to 6 [M(20)] 6 ;Number 6 is placed in M(20) [M(20)] [M(6)];Contents of location (6) are copied into location (20) [M(20)] [M(6)]+3;Read location (6) add 3 and store result in location (20)

4. An address path represents highways along which addresses flow from one part of the CPU to another D0 is data register storing temporary results ALU performs arithmetic and logic operations

5. The FETCH phase in RTL [MAR] [PC];Copy contents of PC to MAR [PC] [PC]+1;Increment PC [MBR] [M9[MAR])] ;Read the instruction from memory [IR] [MBR] ;Move instructions to IR CU [IR(opcode)];Transmit Opcode to Control Unit The Control Unit enables the CPU to carry out the instruction currently in the instruction register (IR). In other words translating the bit pattern into a sequence of actions taking place during the execution of the instruction

6. INTERNAL STRUCTURE OF A PRIMITIVE CPU USING FLIP FLOPS G4 MODEL THE ADD, D0 1. [MAR]  [PC]; ENABLE G1, clock MAR 1a. INC  [PC] 2. [PC]  INC; Enable G2, clock PC 3. [MBR]  [M([MAR])] Enable Memory (E), R/W = 1, enable G6, G11, clock MBR 4. [IR]  [MBR]; enable G7, clock IR 4a CU  [IR(OPCODE)] 5. [MAR]  [IR(address)] enable G3, clock MAR 6. [MBR]  [M(MAR)]; enable memory, R/W = 1 enable G6, G11, clock MBR (as 3 above) 7. ALU  [MBR] enable G7 7a ALU  [D0] enable G10 8. [DQ]  [ALU] enable G12 clock D0 CLK

7. GATE CONTROL SIGNALMEMORYREGISTERS The Microprogram: When the clock pulses the FF register’s D input is transferred to its output Q where it remains until the next clock pulse. Output from each register can be gated into the bus by enabling the appropriate tri- state buffer. (G1 – G12) If the output of the control unit is seen as signals G1-G12, Memory signals E, R/W/, and 5 clocks going into PC, MAR, MBR, IR and D0, then these can be modelled as a sequence of binary values generated at every new step. We call this the Microprogram and it is shown below.

8. Components of a Microprogrammed Control Unit Address Mapper: Lookup table containing starting address of the microprogram for each of the possible Opcodes. Ie it translates the binary Opcode into a Microprogram to execute Microprogram Counter: Clocked to step through the microprogram memory in sequence Microprogram Memory: Stores basic microinstructions sequences for execution Microinstruction register: This is divided into 4 fields: 1.Next microinstruction address 2.Microprogram counter load control field 3.Condition select field 4.CPU control field

9. Components of a Microprogrammed Control Unit - continued Most of the bits in the microinstruction register belong to the CPU control field. This field controls the flow of information within the CPU by enabling the 3-state gates and clocking signals Microinstruction sequence control is determined by the 3 Left-Hand fields of the microinstruction register NEXT ADDRESS, LOAD CONTTORL CONDITION SELECT By loading the address into the next address field a branch can be made anywhere in the microprogram memory Load control tells the microprogram counter how to get the next address Condition select field, implements the conditonal branches at microinstruction level (through a multiplexer)

10. Designing a CPU Designing a CPU involves a number of stages: Stage 1: Select the CPU size in Bits and Define an instruction set that would be used by the CPU. For the selected number of Bits, consider Add 8 to accumulator how the instruction field would be broken up into its constituent parts to make the Opcode, Addressing Mode, Operand. An example format is as follows: 3 Bits for OPCODE 1 Bit for Addressing Mode Four Bits for OPERAND

11. Define the instruction set Having three bit for the OPCODE allows seven different instructions to be used along with two different addressing modes. The table shown below outlines the sixteen different combinations of OPCODE and addressing mode that make the upper four bits of the instruction. The lower four bits are left to be assigned to either a direct value or memory location.

12. Instruction set - Continued

13. Instruction set - continued

14. Example execution of a simple program: LDA 7; Load accumulator with value 7 STA @ 7 Store this in memory address 7 LDA 5 Load accumulator with value 5 ADD 8 Add 8 to the value in the accumulator STOP Note that initially ALL registers are 0 Every time that we execute an instruction we increment the program counter PC

15. FETCH CYCLE: MODEL THE ADD, D0 1. [MAR]  [PC] 2. [PC]  INC 3. [MBR]  [M([MAR])] Enable Memory ; (E), R/W = 1, clock MBR 4. [IR]  [MBR] clock IR 4a CU  [IR(OPCODE)]

16. 5. [MAR]  [IR(address)] clock MAR 6. [MBR]  [M(MAR)]; enable memory, clock MBR

17. 7. ALU  [MBR] 7a ALU  [D0] 8. [D0]  [ALU] clock D0

18. FETCH CYCLE: REPEATED (STA @ 7) 9.[MAR]  [PC] 10. [PC]  INC 11. [MBR]  [M([MAR])] Enable Memory ; (E), R/W = 1, clock MBR 12. [IR]  [MBR] 12a CU  [IR(OPCODE)]

19. 13. [MAR]  [MBR] ; Value available so prepare MAR for Store

20. 14. [MBR]  [D0] ; Put value to use in addition into MBR

21. FETCH CYCLE: REPEATED (LDA 5) 15.[MAR]  [PC] 16. [PC]  INC 17. [MBR]  [M([MAR])] Enable Memory ; (E), R/W = 1, clock MBR 18. [IR]  [MBR] 18a CU  [IR(OPCODE)]

22. 19. [MAR]  [IR(address)] clock MAR

23. 20.[MBR]  [M(MAR)]; enable memory, clock MBR 21. [MBR]  [D0] ; Put value to use in addition into MBR

24. FETCH CYCLE: REPEATED (ADD) 22.[MAR]  [PC] 23. [PC]  INC 24. [MBR]  [M([MAR])] Enable Memory ; (E), R/W = 1, clock MBR 25. [IR]  [MBR] 25a CU  [IR(OPCODE)]

25. 26. [MAR]  [IR(address)] clock MAR

26. 27. [MBR]  [M(MAR)]; enable memory, clock MBR 28. ALU  [MBR] 29. [D0]  [ALU]

27. FETCH CYCLE: REPEATED (STOP) 30.[MAR]  [PC] 31. [PC]  INC 32. [MBR]  [M([MAR])] Enable Memory ; (E), R/W = 1, clock MBR 33. [IR]  [MBR] 33a CU  [IR(OPCODE)]

28. 34. [MAR]  [MBR] ; Prepare for new cycle