Address of next instruction is in PC Address (MAR) is placed on address bus Control unit issues READ command Result appears on data bus Data from data bus copied into MBR PC incremented by 1 Data (instruction) moved from MBR to IR MBR is now free for further data fetches
BSA X - Branch and Save Address Address of instruction following BSA is saved in X Execution continues from X+1
Each phase decomposed into sequence of elementary micro-operations Such as fetch, indirect, and interrupt cycles. Execute cycle One sequence of micro-operations for each opcode Assume new 2-bit register Instruction cycle code (ICC) designates which part of cycle processor is in ▪ 00: Fetch ▪ 01: Indirect ▪ 10: Execute ▪ 11: Interrupt
Can take many forms, depending on the instruction located in the IR. May Involve transferring data among registers, read/write from memory or I/O, and This cycle may involve transferring data among registers, read or write from memory or I/O.
Define basic elements of processor Describe micro-operations processor performs Determine functions control unit must perform
Electronic Signals that execute instructions In CPU Causes Data Transfer Executes Instructions In Control Bus Sends instructions out to I/O devices Ex: Modem, Soundcard & Video card Sends signals to Memory
MAR to PC Opens Communication Between PC and MAR MBR to Memory Steps Listed: Opens Communication Between MAR and Address Bus Memory gets Read Control Signal Communication open Between Data Bus and MBR
Single internal bus Gates used in order to move through the buss Control Signals will send out electronics signals to guide the transfer of information from the external systems bus Temporary storage in registers are used for the proper functionality of ALU
The control unit inputs signals are a combination of: Opcode Bits. Other signals such as interrupts, or condition codes. Timing info (T1 to Tn). These signals are essential for timing for proper sequencing through instruction cycles.
Instruction register the part of the CPU’s control unit that stores the instruction currently being executed or decoded. Op-code causes different control signals for each different instruction Unique logic for each op-code Decoder takes encoded input and produces single output n binary inputs and 2 n outputs
Clock Repetitive sequence of pulses Useful for measuring duration of micro-ops Must be long enough to allow signal propagation Different control signals at different times within instruction cycle Need a counter with different control signals for t1, t2 etc.
Complex sequencing & micro-operation logic Difficult to design and test Inflexible design Difficult to add new instructions
What are a micro operations ? Why should you not read and write from the same register at the same time ? what are the basic elements of a processor ? what happens when interupts are enabled ? Name 3 sub-cycles for the instruction cycles
How many types of micro-operation? What are the inputs of the control signals? List modern I/O Devices What sends an electronic signals that organizes various processor unit to execute an instruction ? What are advantages of hardware implementation ?