Presentation on theme: "Micro-operations Are the functional, or atomic, operations of a processor. A single micro-operation generally involves a transfer between registers, transfer."— Presentation transcript:
1 Micro-operationsAre the functional, or atomic, operations of a processor.A single micro-operation generally involves a transfer between registers, transfer between registers and external bus, or a simple ALU operation.
2 Micro-operations and the Clock Each clock pulse defines a time unit, which are of equal duration.Micro-operations are performed within this time unit.If multiple micro-operations do not interfere with one another then grouping of micro-operations can be performed within one time unit.Grouping can be performed as long as;Proper sequence of events are followedPC MAR must be done first in order for MEMORY MDRConflicts are avoidedMEMORY MDR can not be in the same time unit as MDR IR
3 The Fetch CycleConsists of three time units and four micro-operations.Each micro-operation involves the movement of data into or out of a register.
4 The Indirect CycleOccurs if the instruction specifies an indirect address.Consists of three time unit and three micro-operations.Data is transferred to the MAR from the IR, which is used to fetch the address of the operand, the IR is then updated from MDR so it contains a direct address rather than indirect.
5 The Interrupt CycleOccurs if any enabled interrupts have occurred at the completion of the execute cycle.The contents of the PC are transferred to the MDR, so that they can be saved for return from the interrupt.MAR is loaded with the address at which the contents of the PC are to be savedPC is loaded with the address at the start of the interrupt routine.Final step is to store the MDR into MEMORY.
6 The Execute CycleExecute cycle is not as predictable as other cycles (fetch, indirect, or interrupt).Number of time units and micro-operations varies for every execution cycle.Example; ADD R1, XThe following execute cycle adds the contents of the location X to register R1.
7 Instruction CycleEach phase decomposed into sequence of elementary micro-operations (fetch, indirect, and interrupt cycles)Execute cycleOne sequence of micro-operations for each opcodeNeed to tie sequences of micro-operations togetherAssume new 2-bit registerInstruction cycle code (ICC) designates which part of cycle the processor is in:00: Fetch 10: Execute01: Indirect 11: Interrupt
9 Functional Requirements Define basic elements of processorDescribe micro-operations processor performsDetermine functions control unit must performBasic Elements of the ProcessorALU External data paths Control UnitRegisters Internal data paths
10 Types of Micro-operation Transfer data between registersTransfer data from register to externalTransfer data from external to registerPerform arithmetic or logical operationsFunctions of Control UnitSequencingCauses the processor to step through a series of micro-operationsExecutionCauses the performance of each micro-operationThis is done using Control Signals
12 Control Signals - Input ClockOne micro-instruction (or set of simultaneous micro instructions) per clock pulse.Instruction registerOp-code of the current instructionDetermines which micro-instructions are performedFlagsDetermines the status of the processorResults of previous ALU operationsControl Signals from control busInterruptsAcknowledgements
13 Control Signals - Output Control Signals within the processorCause data movementActivate specific ALU functionsControl Signals to control busTo memoryTo I/O modules
15 PROCESSOR ORGANIZATION Organization is how features are implementedControl signals, interfaces, memory technology.e.g. Is there a hardware multiply unit or is it done by repeated addition
16 Internal Organization Usually a single internal busUsing single bus simplifies & saves spaceGates control movement of data onto and off the busControl signals control data transfer to and from external systems busTemporary registers needed for proper operation of ALU
19 Fetch Sequence (symbolic) t1: MAR <- (IRaddress) address field of IRt2: MBR <- (memory)t3: Y <- (MBR)t4: Z <- (AC) + (Y)t5: AC <- (Z)
20 CPU Clock Clock Repetitive sequence of pulses Useful for measuring duration of micro-opsMust be long enough to allow signal propagationDifferent control signals at different times within instruction cycleNeed a counter with different control signals for t1, t2 etc.
22 Hardwired Implementation Control unit inputsFlags and control busEach bit means somethingInstruction registerOp-code causes different control signals for each different instructionDecoder takes encoded input and produces single outputn binary inputs and 2n outputs
27 Review Questions A single micro-operation generally involves? A transfer between registers, transfer between a register and an external bus, or a simple ALU operation.What is the main purpose of grouping micro-operations together?To save time.
28 What are the basic tasks of a control unit? Sequencing & ExecutionWhat are the inputs of a control unit?Clock, IR, Flags, and control signals from control bus.What is the control signal?What is a hardwired Implementation?Each intruction cycle is divided from 1 to 5 machince cycle; each machine cycle into turn is divided any where from 3 to 5 states.The y register is used as temporary storage for the ALU and the X register is used a tempory output storage.