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ARITHMETIC LOGIC SHIFT UNIT S3 S2 S1 S0CinOperation Function 0 0 0 00F = A Transfer A 0 0 0 01F = A + 1 Increment A 0 0 0 10F = A + B Addition 0 0 0 11F.

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Presentation on theme: "ARITHMETIC LOGIC SHIFT UNIT S3 S2 S1 S0CinOperation Function 0 0 0 00F = A Transfer A 0 0 0 01F = A + 1 Increment A 0 0 0 10F = A + B Addition 0 0 0 11F."— Presentation transcript:

1 ARITHMETIC LOGIC SHIFT UNIT S3 S2 S1 S0CinOperation Function F = A Transfer A F = A + 1 Increment A F = A + B Addition F = A + B + 1 Add with carry F = A + B’ Subtract with borrow F = A + B’+ 1 Subtraction F = A - 1 Decrement A F = A TransferA XF = A  B AND XF = A  B OR XF = A  B XOR XF = A’ Complement A 1 0 X XXF = shr A Shift right A into F 1 1 X XXF = shl A Shift left A into F Shift Microoperations Arithmetic Circuit Logic Circuit C C 4 x 1 MUX Select F S3 S2 S1 S0 B A i A D A E shr shl i+1 i i i i-1 i i

2 BASIC COMPUTER REGISTERS List of Registers DR 16 Data Register Holds memory operand AR 12 Address Register Holds address for memory AC 16 Accumulator Processor register IR 16 Instruction Register Holds instruction code PC 12 Program Counter Holds address of instruction TR 16 Temporary Register Holds temporary data INPR 8 Input Register Holds input character OUTR 8 Output Register Holds output character Registers in the Basic Computer 110 PC 150 IR 150 TR 70 OUTR 150 DR 150 AC 110 AR INPR 07 Memory 4096 x 16 CPU

3 Fundamental Concepts Processor fetches one instruction at a time and perform the operation specified. Instructions are fetched from successive memory locations until a branch or a jump instruction is encountered. Processor keeps track of the address of the memory location containing the next instruction to be fetched using Program Counter (PC). Instruction Register (IR) Mr. Mukul Varshney

4 PROCESSOR REGISTERS Instruction codes A processor has many registers to hold instructions, addresses, data, etc The processor has a register, the Program Counter (PC) that holds the memory address of the next instruction – Since the memory in the Basic Computer only has 4096 locations, the PC only needs 12 bits In a direct or indirect addressing, the processor needs to keep track of what locations in memory it is addressing: The Address Register (AR) is used for this – The AR is a 12 bit register in the Basic Computer When an operand is found, using either direct or indirect addressing, it is placed in the Data Register (DR). The processor then uses this value as data for its operation The Basic Computer has a single general purpose register – the Accumulator (AC)

5 PROCESSOR REGISTERS Instruction codes The significance of a general purpose register is that it can be used for loading operands and storing results – e.g. load AC with the contents of a specific memory location; store the contents of AC into a specified memory location Often a processor will need a scratch register to store intermediate results or other temporary data; in the Basic Computer this is the Temporary Register (TR) The Basic Computer uses a very simple model of input/output (I/O) operations – Input devices are considered to send 8 bits of character data to the processor – The processor can send 8 bits of character data to output devices The Input Register (INPR) holds an 8 bit character gotten from an input device The Output Register (OUTR) holds an 8 bit character to be send to an output device

6 Instruction Format A computer usually have a variety of instruction code formats. It is the function of control unit within the CPU to interpret each instruction code and provide the necessary control functions needed to process the instruction. The format of an instruction is depicted by a rectangular box. The bits of the instruction are divided into groups called fields. The most common fields found in instruction format are: 1) An operation code field that specifies the operation to be performed. 2) An address field that designates a memory address or a processor register. 3) A mode field that specifies the way the operands or the effective address is determined. OpcodeAddressMode Mr. Mukul Varshney

7 – Instruction Code Formats : Memory-reference instruction – Opcode = 000  110 » Register-reference instruction – Input-Output instruction –, I Opcode Address I=0 : Direct, I=1 : Indirect Register Operation I/O Operation Computer Instruction Reading this table: the presented code is for any instruction that has 16 bits. The xxx represents don’t care ( any data for the first 12 bits). Example 7002 for is a hexadecimal code equivalent to Which means B 1 (Bit 1) is set to 1 and the rest of the first 12 bits are set to zeros.

8 Instruction cycle The control unit of a computer is designed to go through an instruction cycle that is divided into three major phases: 1) Fetch the instruction from memory 2) Decode the instruction 3) Execute the instruction PC holds the address of the instruction to be executed next and incremented each time an instruction is fetched from memory. The decoding determines the operation to be performed, the addressing modes and the location of the operands. The computer than executes the instruction Mr. Mukul Varshney

9 Instruction cycle The instruction execution cycle can be clearly divided into three different parts Fetch Cycle The fetch cycle takes the address required from memory, stores it in the instruction register, and moves the program counter on one so that it points to the next instruction. Fetch Cycleinstruction register PC contains address of next instruction Address moved to MAR Address placed on address bus Control unit requests memory read Result placed on data bus, copied to MBR, then to IR Meanwhile PC incremented by 1 Decode Cycle Here, the control unit checks the instruction that is now stored within the instruction register. It determines which opcode and addressing mode have been used, and as such what actions need to be carried out in order to execute the instruction in question. Decode Cycleinstruction register Execute Cycle The actual actions which occur during the execute cycle of an instruction depend on both the instruction itself, and the addressing mode specified to be used to access the data that may be required Execute Cycle Mr. Mukul Varshney

10 Instruction cycle Mr. Mukul Varshney The fetch & decode phases of the instruction cycle consists of the following microoperations synchronized with the timing signals (clocking principle). Timing signal microoperations T0: AR  PC T1: IR  M[AR], PC  PC + 1 T2: D0,..., D7  Decode IR(12-14), AR  IR(0-11), I  IR(15)

11 Mr. Mukul Varshney T0: Since only AR is connected to the address inputs of memory, the address of instruction is transferred from PC to AR. 1. Place the content of PC onto the bus by making the bus selection inputs S2S1S0 = Transfer the content of the bus to AR by enabling the LD input to AR ( AR  PC ). T1: The instruction read from memory is then placed in the instruction register IR. At the same time, PC is incremented to prepare for the address of the next instruction. 1. Enable the read input of the memory. 2. Place the content of memory onto the bus by making the bus selection inputs S2S1S0 = 111. (Note that the address lines are always connected to AR, and we have already placed the next instruction address in AR.) 3. Transfer the content of the bus to IR by enabling the LD input to IR ( IR  M[AR] ). 4. Increment PC by enabling the INR input of PC ( PC  PC + 1 ). T2: The operation code in IR is decoded; the indirect bit is transferred to I; the address part of the instruction is transferred to AR. (See the common bus skeleton diagram.)

12 Mr. Mukul Varshney Similar circuits are used to realize the microoperations at T2. At T3, microoperations which take place depend on the type of instruction. The four different paths are symbolized as follows, where the control functions must be connected to the proper inputs to activate the desired microoperations. Control function Microoperation D7’IT3: AR  M[AR], indirect memory transfer D7’I’T3: Nothing, direct memory transfer D7I’T3: Execute a register-reference instruction D7IT3: Execute an I/O instruction When D7’T3 = 1 (At T3 & IR(12-14)  111), the execution of memory- reference instructions takes place with the next timing variable T4.

13 Mr. Mukul Varshney

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