1. EE141 Project: 32x32 SRAM Abhinav Gupta, Glen Wong Optimization goals: Balance between area and performance Minimize area without sacrificing performance

2. SRAM Cell Design 6-T SRAM Cell Modified provided SRAM cell to decrease area from 38.08 μ m 2 to 31.68 μ m 2. Inverter PMOS: 0.36 μ m Inverter NMOS: 1.08 μ m Pass Transistor: 0.54 μ m

3. Read and Write Noise Margins Read Noise Margin AnalysisWrite Noise Margin Analysis Read Voltage Rise: 284mV Write Cell Voltage: 181mV

4. Decoder Design Each input to the Decoder was buffered via inverters due to branching. The split SRAM allows for reduced C fixed. The decreased size of SRAM cell enables lower load capacitance. Calculated Delay: 624.65ps

5. Decoder Implementation Layout of final Decode Stage on the left consists of 3 inputs and 1 output. Simulated delay of full decoder: 547.51ps

6. Adder Design Ripple-Carry Adder Chain Produces both Sum and its complement values Critical Path consists of initial carry generation to evaluation of MSB sum value Calculated Delay: 690.5ps

7. Adder Implementation Layout of Full Adder consists of 16 inputs and 10 outputs and is directly connected to the pre-decode stage. Simulated delay of full decoder: 886.94ps

8. SRAM Array Design Split SRAM Array to save wire capacitance between pre- decode and final-decode stages. Reduced SRAM Cell Size without decreasing transistor sizes Minimizing area of cell, and decode stage without affecting delay/performance.

9. SRAM Array Layout Pre-Charge Devices only one side of SRAM (other side internally connected). Output Buffers only on one side of SRAM as well. Total Simulated Delay: 1.539ns Overall Area: 49,607 μ m 2.