1. ECE 353 Introduction to Microprocessor Systems Michael J. Schulte Week 9

2. Topics I/O port basics I/O ports with MSI devices  P compatible devices Address decoding for isolated and memory-mapped I/O Conditional I/O 80C188EB integrated I/O unit 82C55A PPI

3. I/O Port Basics I/O subsystems allow CPU to interact with the outside world Input, output, and combined I/O blocks Input ports Byte Word Output ports Byte Word Unconditional I/O

4. MSI I/O Ports Medium Scale Integration (MSI) circuits are available to construct ports Simple byte input ports can be constructed from… Octal buffers Octal registers Simple byte output ports can be constructed from octal latches

5.  P Compatible I/O Devices Complex I/O devices typically require complex interface and control logic  P compatible I/O devices have the necessary logic built in to the device itself Interface designed to be reasonably compatible with many microprocessor buses Need to add decoding/selection logic Examples Device controllers Used to control complex I/O devices (LCD, disk drives, etc.) Generic model

6. I/O Address Decoding I/O address decoding determines the logical location of the I/O device Isolated I/O Memory-mapped I/O Input vs. output ports Same address does not guarantee same function! Device select pulses Wait states Using the CSU with I/O devices

7. I/O Address Decoding (cont.) PAL/PLA Decoders Nonspecific I/O strobes /IOW /IOR Linear selection Conventional decoders Device select strobes Cascading

8. Conditional I/O Conditional vs. unconditional transfers Hardware example Polling Overhead Flags / semaphores Wait loops Timeouts Software exercise Possible race condition

9. 80C188EB Integrated I/O Unit Port 1 Functions Port 2 Functions Bidirectional pin structure Synchronizer Programming Port Control Register Port Direction Register Port Data Latch Register Port Pin State Register

10. 82C55A Programmable Peripheral Interface (PPI) LSI device providing 24 bits of I/O Logical organization Block diagram Software configurable ports Three modes of operationmodes  Mode 0 Basic Input/Output ports  Mode 1 Strobed Input/OutputInputOutput  Mode 2 Bidirectional data bus Bit set/reset capability

11. Real-World Example Interface the MAX154 8-bit, 4-channel ADC to the 80C188EB Hardware interface  Use /GCS0 at I/O address 1000h (CSU)CSU  Poll conversion status using Port 2.Port 2 P2CON / P2DIR / P2LTCH / P2PIN P2CONP2DIRP2LTCHP2PIN Software interfacing  Write a procedure that does an ADC conversion and then reads the ADC value using mode 1  Input: AL = ADC input channel to use (0-3)  Output: ADC value returned in AL What about mode 0? Timing?

12. Byte Input Port Example

13. Byte Output Port Example

14. 74HC540/541

15. 74HC573

16. 74HC574

17. MAX1200

18. AD7865

19. Generic Device Controller (Fig 12.3-2)

20. Hitachi HD44780U LCD Controller

21. Port 1 Functions

22. Port 2 Functions

23. Bidirectional Port Pin

24. Port Control Register

25. Port Direction Register

26. Port Data Latch Register

27. Port Pin State Register

28. Conditional I/O Exercise Write a procedure to read data from an input device like the hardware example. Assume that the flag is a READY signal (active high). If the device does not become ready after 1 million polling attempts, return with the carry flag set, otherwise, return with the data in AL and the carry flag cleared.

29. 82C55A Block Diagram

30. 82C55A Modes of Operation

31. 82C55A Mode 1 Input

32. 82C55A Mode 1 Output

33. Chip- Select Start Reg

34. Chip- Select Stop Register - Part 1

35. Chip- Select Stop Register - Part 2

36. Conditional I/O Example

37. Synchronization