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Dr A Sahu Dept of Computer Science & Engineering IIT Guwahati.

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Presentation on theme: "Dr A Sahu Dept of Computer Science & Engineering IIT Guwahati."— Presentation transcript:

1 Dr A Sahu Dept of Computer Science & Engineering IIT Guwahati

2 Hierarchy of I/O Control Devices 8155 I/O + Timer 8155 I/O + Timer 8255 I/O 8255 I/O 8253/54 Timer 8253/54 Timer 2 Port (A,B), No Bidirectional HS mode (C) 4 mode timer 2 Port (A,B) A is Bidirectional HS mode (C) Extra controls 6 mode timer 8259 Interrupt controller 8259 Interrupt controller 8237 DMA controller 8237 DMA controller 8251 Serial I/O USART controller 8251 Serial I/O USART controller

3 8155 I/O Interface & Timer – Dedicated I/O interface (8255) – Dedicated Timer (8254/8253) 8255 Ports and mode of operations Interfacing A/D Converter using Handshake mode using 8255

4 IO Capability: – 2kbits static RAM 256x8 – 2 programmable 8 bit I/O ports – 1 programmable 6 bit I/O port Timer Capability: – 1 programmable 14 bit binary counter/timer – 4 Modes RAM Port A Port A Port B Port B Port C Port C Timer MSB LSB Timer MSB LSB PA0- PA7 PB0- PB7 PC0-PC5 Timer Out Reset in RD WR AL E CECE IO/M AD0-AD7 Timer CLK Mode 00 Mode 01 Mode 10 Mode 11 N/2 N NN D7D6D5D4D3D3 D2D1D0 Timer Command IEBIEAPCPBPA ALTALT D3D3 D2D2 PC5PC4PC3PC2PC1PC0 100IN 201OUT 310 STB A BF A INTR A 411STB B BF B INTR B STB A BF A INTR A

5 3 to 8 Decoder CWR Port A Port A Port B Port B Port C Port C Timer MSB LSB Timer MSB LSB Latch Clock for timer PA0-PA7 PB0-PB7 PC0-PC5 Timer Out A0 A1 A2 ALE AD0-AD7 A0-A7 D7-D CE b A2A1A0Port (ALE high, AD0=A0) 000Command /Status Register 001PA 010PB 011PC 100Timer LSB 101Timer MSB

6 Group A Control Group A Control Group B Control Group B Control Read Write Control Logic Read Write Control Logic Data Bus Buffer Data Bus Buffer Gr A Port A (8) Gr A Port A (8) Gr A Port C (H 4) Gr A Port C (H 4) Gr B Port C (L 4) Gr B Port C (L 4) Gr B Port B (8) Gr B Port B (8) I/O PA7-PA0 I/O PC7-PC4 I/O PC3-PC0 I/O PB7-PB0 8 bit Internal Data Bus Bi directional Data Bus D7-D0 RD b WR b A1 A0 RESET CS b Block Diagram of 8255 CS b A1A0Sel 000Port A 001Port B 010Port C 011CRW

7 Ports & Modes in 8255 Port C D7 D6 D5 D4 D3 D2 D1 D BSR Mode Bit Set/Reset BSR Mode Bit Set/Reset 8255 Port B C U C L Port A I/O Mode Mode 0 Simple I/O for Ports A, B & C Mode 0 Simple I/O for Ports A, B & C Mode 1 HS mode for Ports A and/or B Port C bits are used for HS Mode 1 HS mode for Ports A and/or B Port C bits are used for HS Mode 2 Bidirectional Data mode for Port A B can in mode 0/1 Port C bits are used for HS Mode 2 Bidirectional Data mode for Port A B can in mode 0/1 Port C bits are used for HS BSR Mode Bit Set/Reset For Port C No Effect on I/O Mode BSR Mode Bit Set/Reset For Port C No Effect on I/O Mode 0/1

8 Ports & Modes in 8255 : Control register D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D Port A – 1 Input 0 output Mode select: 00 mode 0; 01 mode 1; 0x mode 2 1 – mode select 0 – bit set/reset Port C(U) – 1 Input 0 output Mode select: 0 mode 0; 1 mode 1 Port B – 1 Input 0 output Port C(L) – 1 Input 0 output Group A Group B

9 I/O port Addressing 8255 CS b A1 A0 RD b WR b A7 A6 A5 A4 A3 A2 A1 A0 IOR b IOW b Reset Port A=80H Port C=82H Port B=81H CS b A1 A0HEX AddressPort A7 A6 A5 A4 A3 A A1 A0 0 = 80HA 0 1=81HB 1010=82HC 1=83HControl Register

10 BSR (Bit Set or Reset Mode) Set/Reset bit of Port C Heavily used for HS and Interrupt mode BSR Control word – To set PC7= (0FH) – To reset PC7= (0EH) – To set PC3 = (07H) D7D6D5D4D3D2D1D0 0 BSR Mode Not used, So (000) Bit SelectS/R (1/0)

11 Ports Control register controls the overall operation of 8255 All three ports A, B and C are grouped into two Group B Group B Group A Port A Upper C Port B Lower C

12 Operation modes 8255 has three modes: - mode 0: basic input-output - mode 1: strobed input-output - mode 2: strobed bidirectinal bus I/O In mode 0 - two 8-bit ports and two 4-bit ports - any port can be input or output - Outputs are latched, inputs are not latched

13 Mode 0 Port A Upper C Port B Lower C

14 Operation mode 1 In mode 1: -three ports are divided into two groups -each group contains one 8-bit port and one 4-bit control/data port - 8-bit port can be either input or output and both latched - 4-bit port used for control and status of 8- bit data port

15 Mode 1 Group B Group B Group A Port A Upper C Port B Lower C

16 In mode 2 - only port A is used - port A becomes an 8-bit bidiectional bus - port C acts as control port (only pins PC3-PC7 are used) Operation mode 2

17 Mode 2 Group B Group A Port A C7-C3 Port B

18 Programming 8255  Mode 2: — Port A is programmed to be bi-directional — Port C is for handshaking — Port B can be either input or output in mode 0 or mode 1 PA[7:0] OBF A ACK A INTR A PC4 PC6 PC7 STB A IBF A PC0 PC3 PC PC0 PB[7:0] In Out Mode 0 STB B OBF B IBF B ACK B INTR B Mode 1

19 R S Gaonkar, “Microprocessor Architecture”, Chapter 15

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