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ECE 353 Introduction to Microprocessor Systems Michael G. Morrow, P.E. Week 13.

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Presentation on theme: "ECE 353 Introduction to Microprocessor Systems Michael G. Morrow, P.E. Week 13."— Presentation transcript:

1 ECE 353 Introduction to Microprocessor Systems Michael G. Morrow, P.E. Week 13

2 Topics Serial I/O Serial data transfer concepts Asynchronous and synchronous transfers UARTs  UART Interrupts Circular buffering RS-232 and flow control ADuC7026 Serial Peripherals UART SPI I 2 C

3 Serial I/O Concepts Serial communication transmits data one bit at a time. Why? Data transfers over long distances Reduced pin and interconnection count Easier to route with switches Eliminates parallel bus skew issues Terminology Communications channel Simplex vs. duplex Transmission rates Information codes Data Frames

4 Serial Communications Concepts - Morse Code A.- N -. 1.----..-.-.- B -... O --- 2..---, --..-- C -.-. P.--. 3...-- ?..--.. D -.. Q --.- 4....- ( -.--. E. R.-. 5..... ) -.--.- F..-. S... 6 -.... - -....- G --. T - 7 --... ".-..-. H.... U..- 8 ---.. _..--.- I.. V...- 9 ----. '.----. J.--- W.-- 0 ----- : ---... K -.- X -..- / -..-. ; -.-.-. L.-.. Y -.-- +.-.-. $...-..- M -- Z --.. = -...-

5 Asynchronous vs. Synchronous Asynchronous Communication No common clock signal between transmitter and receiver Synchronization must be established on a per frame basis Example – RS232 Synchronous Communication Clock is transmitted in addition to data, or is recovered from data signalrecovered from data signal Often includes a framing signal as well Example – I 2 S Example – I 2 S

6 Asynchronous Data Transfer RS-232 signal phases Idle Start bit Data Parity Stop bit – channel returns to idle condition Idle or Start next frame

7 UARTs Universal Asynchronous Receiver- Transmitter Basic UART construction Practical UARTs  Complex I/O device functionality encapsulated behind a register interfaceregister interface Control Status Data  16550-class UART Organization 16550-class UART Organization FIFOs MODEM control signals

8 UART Interrupts UARTs often can generate interrupts for a number of conditions Receive data ready Receive data error  Framing, parity, overrun Modem signal status changes Transmitter buffer and/or shifter empty  Issues using the transmit interrupt Edge versus level interrupts Loading the transmitter queue

9 Circular Buffering Implement simple FIFO queueing in software to minimize data movement. Some CPUs (especially DSPs) implement circular addressing modes in hardware for speed.

10 RS-232 RS-232 is one of many physical-level standards for serial communications. Selected serial communications standards RS-232 defines many aspects of the serial data channel Equipment definitions Connector construction and pin-outspin-outs Modem control signals Signal levels RS-232 line drivers and receiversline drivers and receivers

11 Flow Control A serial channel may deliver data faster than the receiving device can process. Flow control gives the receiver a way to signal the transmitter to stop transmission. Flow control can be implemented as Software  XON/XOFF flow control protocol Hardware  RTS/CTS

12 ADuC7026 Serial Peripherals There are 4 serial peripherals on the ADuC7026; a UART and 3 synchronous ports (SPI and I 2 C) There are ten pins that are used by the serial peripherals in two modes

13 ADuC7026 UART COMCON0 Basic frame configuration Baud rate Basic baud rate divider Fractional baud rate divider

14 ADuC7026 SPI Port The Serial Peripheral Interface (SPI) port can be configured as a master or slave (shown below) SPI consists of 2 unidirectional data lines, a clock line, and a chip select line The master generates the clock and select signals, so it controls when/if transfers occur

15 ADuC7026 I 2 C Ports The Inter-Integrated Circuit (I 2 C) ports can operate as master or slave I 2 C supports multi-master buses using just 2 bidirectional lines (clock and data)  Both use open-drain drivers and pull-up resistors  Collisions can occur without damage – recognized when a line will not return high after it is released

16 Wrapping Up Quiz #3 on Thursday, May 3 rd at 7:15pm in 2255EH Homework #7 is due Friday, May 11 th Final Exam on Wednesday, May 16 th, at 12:25pm in room 2255EH. Coverage is over all course material.

17 Asynchronous Communications - RS232 Framing Back What do you need to know in order to figure out what the data is?

18 Synchronous Communications Back frame

19 Clock Recovery Back

20 Serial Communications Standards Back

21 RS-232 Connectors Back

22 RS-232 Signal Levels Back Data signals are shown. Control signals have opposite polarity.

23 MAX221 Back

24 16550-Class UART

25 16550-Class UART Registers Back

26 Basic UART Construction Back


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