1. Clock Distribution Network
Basics
Prof. John Reuben,
VIT University, INDIA

2. Clock signals loaded with highest fan-out
travel over the longest distances
operate at highest speed.
Clock signals
From Facility Location and Clock Tree Synthesis, Jens Uwe Maßberg, Thesis, Universit¨at Bonn

4. Why buffers?
A typical clock distribution structure relies on buffer stages to amplify the clock from the clock generator to the clock sinks
To reduce propagation delay/clock latency(signal propagation delay increases quadratically with wirelength)
The distributed buffers serve the double function of amplifying the clock signals degraded by the distributed interconnect impedances and isolating the local clock nets from upstream load impedances.

5. Terminologies
Clock latency is the amount of time taken by the clock signal to travel from its source(on-chip PLL) to the clocked elements- latches, flip flops and registers(collectively called clock sinks).

6. Clock Skew
clock skew is spatial variation in the arrival time of the clock signals at sinks
Major sources- on-die process variations, loading variations and other unintentional design mismatches
Static uncertainty

7. Clock Jitter
Clock jitter is the temporal variation in the arrival time of the clock signals at sinks.
Major sources- dynamic voltage variations, temperature gradient due to activity variations and jitter in clock generator
Dynamic uncertainty

8. Clock Slew
Clock slew - measure of the reconstruction capability of the buffers in a clock distribution network.
If the buffers are not designed according to the load it has to drive, the clock slews i.e the rise/fall time of the clock deviates from the accepted norm.

9. Topologies Broad classification - Clock Tree and Clock Mesh
The goal of a clock tree is to get the clock signal from a clock source to clock sinks. The relative arrival times, shape, and amplitude of the clock signal at the sinks need to meet certain criteria for the circuit to work correctly. Simple wires are susceptible to influences of signals in nearby wires and their own parasitics among other things that may compromise the integrity the signal and cause the signal arriving at the sinks to be unacceptable. 9

10. Topologies
Buffering, which restores the signal and reduces delay, helps to guarantee the integrity of the clock signal. These are the two steps that are carried out in the clock tree generation steps in the SSHAFT flow. 10

11. Unconstrained Tree
Unconstrained tree is a clock network that is designed with a cost function that minimizes the delay differences across all clock branches.
It doesn’t have any structural matching

12. Balanced Tree
Balanced tree is a tree with structural symmetry and exhibits identical delay, buffer and interconnect segments from the root of the distribution to all branches.
Structural skew- zero

13. Binary Tree
Binary tree is a tree intended to deliver the clock in a balanced manner in either the vertical or horizontal dimension.
This is different from a balanced tree which is designed to span the entire die in both the horizontal and vertical dimensions.

14. Binary tree with cross-links
A binary tree with cross-links is a scheme which is a specific implementation of a binary tree.
Cross-links are inserted at specific points along the tree to equalize clock latency.

15. Combination of topologies

16. Common structures of clock distribution networks including a trunk, tree, mesh, and H-tree

17. Clock Distribution in a processor
Pentium R 4 processor clock distribution using centralized spines with delay matched final branches. Reproduced with permission from [49],copyright 2001 IEEE

19. Clock Network Modeling

20. Elmore Delay

21. Clock network modelling

22. Clock network modelling
telmore,v=CuRu+ Cv(Ru+Rv) +CxRu + Cy(Ru+Rv) + Cz(Ru+Rv)

23. Clock network modelling
telmore,v=CuRu+ Cv(Ru+Rv) +CxRu + Cy(Ru+Rv) + Cz(Ru+Rv)

24. Clock network modelling
telmore,v=CuRu+ Cv(Ru+Rv) +CxRu + Cy(Ru+Rv) + Cz(Ru+Rv)

25. Clock network modelling
telmore,v= Ru (Cu + Cv +Cx+ Cy+ Cz) + Rv (Cv + Cy + Cz )
telmore,u= Ru (Cu + Cv +Cx+ Cy+ Cz)
telmore,v = telmore,u + Rv (Cv + Cy + Cz )

26. Elmore delay In other words, the Elmore delay of a node
is an accumulation of RC product terms from the voltage source to the node of interest.
The RC product term at node k is that of the branch resistance Rk and the total downstream capacitance Ctk
Therefore, in a top-down manner from the voltage source to node i, we can sum up the RC delay of each resistor along the path.
In fact, in a top-down traversal of the tree T, we can compute the Elmore delays for all nodes.

27. References
Clocking in Modern VLSI Systems, Thucydides Xanthopoulos, Editor, Springer 2009
Synthesis of clock and power/ground networks, Chapter 13 of Electronic Design Automation, Morgan Kaufman, 2009