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Published byAlina Harp Modified over 3 years ago

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Advanced Interconnect Optimizations

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Buffers Improve Slack RAT = 300 Delay = 350 Slack = -50 RAT = 700 Delay = 600 Slack = 100 RAT = 300 Delay = 250 Slack = 50 RAT = 700 Delay = 400 Slack = 300 slack min = -50 slack min = 50 Decouple capacitive load from critical path RAT = Required Arrival Time Slack = RAT - Delay

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Timing Driven Buffering Problem Formulation Given –A Steiner tree –RAT at each sink –A buffer type –RC parameters –Candidate buffer locations Find buffer insertion solution such that the slack at the driver is maximized

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Candidate Buffering Solutions

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Candidate Solution Characteristics Each candidate solution is associated with –v i : a node –c i : downstream capacitance –q i : RAT v i is a sink c i is sink capacitance v is an internal node

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Van Ginneken’s Algorithm Candidate solutions are propagated toward the source Dynamic Programming

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Solution Propagation: Add Wire c 2 = c 1 + cx q 2 = q 1 – rcx 2 /2 – rxc 1 r: wire resistance per unit length c: wire capacitance per unit length (v 1, c 1, q 1 ) (v 2, c 2, q 2 ) x

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8 Solution Propagation: Insert Buffer c 1b = C b q 1b = q 1 – R b c 1 – t b C b : buffer input capacitance R b : buffer output resistance t b : buffer intrinsic delay (v 1, c 1, q 1 ) (v 1, c 1b, q 1b )

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Solution Propagation: Merge c merge = c l + c r q merge = min(q l, q r ) (v, c l, q l )(v, c r, q r )

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Solution Propagation: Add Driver q 0d = q 0 – R d c 0 = slack min R d : driver resistance Pick solution with max slack min (v 0, c 0, q 0 ) (v 0, c 0d, q 0d )

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Example of Solution Propagation (v 1, 1, 20) 22 v1v1 v1v1 (v 2, 3, 16) r = 1, c = 1 R b = 1, C b = 1, t b = 1 R d = 1 (v 2, 1, 12) v1v1 (v 3, 5, 8) v1v1 (v 3, 3, 8) slack = 5slack = 3 Add wire Insert buffer Add wire Add driver

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12 Example of Merging Left candidates Right candidates Merged candidates

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Solution Pruning Two candidate solutions –(v, c 1, q 1 ) –(v, c 2, q 2 ) Solution 1 is inferior if –c 1 > c 2 : larger load –and q 1 < q 2 : tighter timing

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Pruning When Insert Buffer They have the same load cap C b, only the one with max q is kept

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15 Generating Candidates (1) (2) (3) From Dr. Charles Alpert

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16 Pruning Candidates (3) (a) (b) Both (a) and (b) “look” the same to the source. Throw out the one with the worst slack (4)

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17 Candidate Example Continued (4) (5)

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18 Candidate Example Continued After pruning (5) At driver, compute which candidate maximizes slack. Result is optimal.

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19 Merging Branches Right Candidates Left Candidates

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20 Pruning Merged Branches Critical With pruning

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21 Van Ginneken Example (20,400) (30,250) (5, 220) Wire C=10,d=150 Buffer C=5, d=30 (20,400) Buffer C=5, d=50 C=5, d=30 Wire C=15,d=200 C=15,d=120 (30,250) (5, 220) (45, 50) (5, 0) (20,100) (5, 70)

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22 Van Ginneken Example Cont’d (20,400) (30,250) (5, 220) (45, 50) (5, 0) (20,100) (5, 70) (5,0) is inferior to (5,70). (45,50) is inferior to (20,100) (20,400) (30,250) (5, 220) (20,100) (5, 70) (30,10) (15, -10) Pick solution with largest slack, follow arrows to get solution Wire C=10

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Basic Data Structure (c 1, q 1 )(c 2, q 2 )(c 3, q 3 ) Sorted list such that c 1 < c 2 < c 3 If there is no inferior candidates q 1 < q 2 < q 3 Worse load cap Better timing

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24 Prune Solution List (c 1, q 1 )(c 2, q 2 )(c 3, q 3 ) Increasing c q 1 < q 2 ? (c 4, q 4 ) q 3 < q 4 ? Y N Prune 2 q 1 < q 3 ? q 2 < q 3 ? Y q 3 < q 4 ? Y Prune 3 q 1 < q 4 ? N Prune 3 N N Prune 4 N q 2 < q 4 ?

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25 Pruning In Merging (c l1, q l1 ) (c l2, q l2 ) (c l3, q l3 ) (c r1, q r1 ) (c r2, q r2 ) q l1 < q l2 < q r1 < q l3 < q r2 Merged candidates (c l1 +c r1, q l1 ) (c l2 +c r1, q l2 ) (c l3 +c r1, q r1 ) (c l3 +c r2, q l3 ) (c l1, q l1 ) (c l2, q l2 ) (c l3, q l3 ) (c r1, q r1 ) (c r2, q r2 ) (c l1, q l1 ) (c l2, q l2 ) (c l3, q l3 ) (c r1, q r1 ) (c r2, q r2 ) (c l1, q l1 ) (c l2, q l2 ) (c l3, q l3 ) (c r1, q r1 ) (c r2, q r2 ) Left candidates Right candidates

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Van Ginneken Complexity Generate candidates from sinks to source Quadratic runtime –Adding a wire does not change #candidates –Adding a buffer adds only one new candidate –Merging branches additive, not multiplicative –Linear time solution list pruning Optimal for Elmore delay model

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Multiple Buffer Types (v 1, 1, 20) 22 v1v1 v1v1 (v 2, 3, 16) r = 1, c = 1 R b1 = 1, C b1 = 1, t b1 = 1 R b2 = 0.5, C b2 = 2, t b2 = 0.5 R d = 1 (v 2, 1, 12) v1v1 (v 2, 2, 14)

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Chapter 6 Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved. High-Speed CMOS Logic Design.

Chapter 6 Copyright © 2004 The McGraw-Hill Companies, Inc. All rights reserved. High-Speed CMOS Logic Design.

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