1. Chapter 3 : Top Level View of Computer Functions Basic CPU function, Interconnection, Instruction Format and Interrupt

2. Agenda 1.Basic Function of a computer. The view of software execution. Before, we discussed “micro program” (hardware), now we discuss software 2.“Picture” of program in memory : machine format, hexa-decimal format, mnemonic codes 3.Basic Instruction Format and its corresponding CPU components (PC, IR) 4.Interconnection structures (highlight) 4. Interrupt : a way of sharing CPU time amongst different devices attached to it (hardware discussion)

3. 3.2. The Computer Function Basic function : program execution Program : Set of instructions stored in memory CPU fetches the instructions, one at a time and executes them one by one, according to the operation code Simple way of thinking : two steps of instruction processing, fetch and execute Actually, instruction execution may involve a number of steps The processing time required for execution of a single instruction is called an instruction cycle time

4. 3.2 Computer Function : Basic Instruction Cycle Fetch Next Instruction Execute Instruction START HALT Fetch Cycle Execute Cycle

5. 3.2 Function - Fetch and Execute Cycles An instruction is fetched to CPU using the address in PC (Program Counter) Unless told otherwise, CPU always increment PC after fetching an instruction. PC points to next instruction. Example : For instance PC is set to 300. After a fetch cycle, the PC is incremented by 1. PC points to location 301. This activity happens at PC unless CPU execute a jump instruction. The fetched instruction is loaded into IR (Instruction Register) in the CPU. The instruction is in the form of binary code.

6. 3. System Bus 3.1. Computer Components : MAR MBR I/O AR I/O BR CPUMemory I/O Module Buffers 0 1 2 n Instruction... Data IR PC

7. 3. System Bus 3.1. Computer Components : MAR MBR I/O AR I/O BR CPUMemory I/O Module Buffers 0 1 2 n Instruction... Data IR PC

8. 3. System Bus 3.1. Computer Components : MAR MBR I/O AR I/O BR CPUMemory I/O Module Buffers 0 1 2 n Instruction... Data IR PC

9. 3.2 Function - Instruction format & codes Consider a hypothetical machine : OpCodeAddress 0 3 4 15 a. Instruction Format S 0 1 15 Magnitude b. Integer Format Program Counter (PC) = Address of Instruction Instruction Register (IR) = Instruction being Executed Accumulator (AC) = Temporary Storage c. Inter CPU Registers 0001 = Load AC from Memory 0010 = Store AC to Memory 0101 = Add to AC from Memory d. Partial List of Opcodes

10. 3.2 Function - Example of program execution Word length = 16 bit: 1. Assume PC contains 300. This content of location 300 is loaded into IR ( First PC to MAR, READ, Memory xfer to MBR and finally MBR to IR). 2. The first 4 bit in IR indicate that AC is to to be loaded. The next 12 bits (940) specify operand address. 3. PC is incremented, next instruction is fetched 4. Old content of AC & content of location 940 are added, stored in AC. 5. PC is incremented, next instruction is fetched. 6. The content of AC are stored in location 941. OpCode 0 3 4 15 Address (12 bits)

11. Instructions and Data in Memory Instrcution (16 bits)Instruction & DataMemory (hexadecimal)Address ----------------------------------------------------------------------------------- 00011001010000001940 300 01011001010000015941 301 00101001010000012941 302 00000000000000110003 940 00000000000000100002 941 instructions data

12. 3.2 Function - execution in hypothetical machine

13. 3.2. Interrupt Interrupt is a mechanism whereby a particular computer system component (I/O devices, Real Time Clock, Memory Unit, etc) could ask for CPU attention due to some very important condition occuring

14. Interrupt in Computer Systems Governed by : Operating Systems Interrupt : Mechanism to alert CPU, something needs its attention

15. 3.2 Interrupts Table 3.1 : Classes of Interrupts -------------------------------------------------------------------------- Program Generated by some condition that occurs as a result of an instruction execution, such as arithmetic overflow, division by zero, attempt to execute illegal instruction, reference outside user’s allowed memory space. Timer Generated by timer within the processor. This allows the O/S to perform certain function on regular basis. I/O Generated by an I/O controller, to signal normal completion of an operation or to signal a variety of error conditions Hardware Failure Generated by failure, such as power or memory parity. -----------------------------------------------------------------------------------------

16. Transfer of Control via Interrupts

17. What happen with instruction cycle ? Instruction cycle with interrupt

18. Example of Interrupt chain 0 1 2 3 Priority Encoder Bus Buffers 0 1 2 3 IST IEN VAD To CPU Signal line From CPU Signal line tp CPU Disk Printer FloppyKeyboard I0I0 I1I1 I2I2 I3I3 Mask register Bus Buffer Enable line Interrupt register x y 0 0 0 0 0 0 Mask Register could be set to 0, which disable the possibility of accepting interrupt signal from devices (0 through 3) IEN is a latch, that may be set by the CPU to enable/disable the acceptance of any interrupt form all devices

19. Example of Interrupt chain 0 1 2 3 Priority Encoder Bus Buffers 0 1 2 3 IST IEN VAD Interrupt to CPU Disk Printer FloppyKeyboard I0I0 I1I1 I2I2 I3I3 Mask register Interrupt register 1 1 0 0 0 0 0 0 1111 0101 0101 0101 1 Device 0 interrupt, mask-bit is 1. Interrupt signal reach Priority Encoder, going out with device code 11 (in VAD) Interrupt signal goes further to CPU, using the bottom side of the circuit (red lines)

20. Example of Interrupt chain 0 1 2 3 Priority Encoder Bus Buffers 0 1 2 3 IE IST IEN VAD Interrupt Address (VAD) (Vector) To CPU INTACK from CPU Disk Printer FloppyKeyboard I0I0 I1I1 I2I2 I3I3 Mask register Enable Interrupt register 1 1 0 0 0 0 0 0 1111 0101 0101 0101 1 Interrupt Acknowledged by the CPU (INTACK) Interrupt enable latch is set on (IEN) Interrupt signal, IEN signal and INTACK set the IE AND gate to pass interrupt enable signal to BUS Buffers Enabled by this signal, Bus Buffers send the interrupt address to CPU (the address of interrupt handler)