1. Microcontroller Intel 8051 [I/O Ports]

2. Pin out of the 8051 –40 pin package –32 pins are used for the 4 ports. –V CC / V SS –ALE Address Latch Enable –EA / V PP External Address Program Voltage for EPROM based versions of the 8051. –XTAL1 and XTAL2 Connections for clock crystal. –PSEN “Program Store Enable” –Read signal for external program memory –RST Reset

3. I/O Ports The 8051 has 4 bidirectional 8-bit I/O ports. –Each port is connected to an 8-bit register in the SFR. P0 = 80H, P1 = 90H, P2 = A0H, P3 = B0H –Each port is also connected to an output driver and an input buffer. –All ports are configured for output at reset. Some of the 4 ports have uses in addition to simple I/O. –Ports P0 and P2 double as the 8051’s Address and Data busses. –Port P3 doubles as the 8051’s external control lines for the timers and counters.

4. Port P0 P0 can be used for input or output. The pins of P0 are connected internally to an “open drain” circuit (similar to open collector but using MOS transistors). –Therefore, it must be connected to an external pull-up resistor (10 K  ) to operate properly as an output port. To operate P0 as an input port, it must be programmed by writing 1’s to all of its bits

5. Port 0 with Pull-Up Resistors

6. Dual Role of P0 P0 is also designated as AD0 – AD7 which means that it also doubles as the multiplexed lower 8 bits of the address bus and the 8 bits of the data bus. P0 will be used in this manner when accessing external memory. Program or data. –ALE is used to differentiate when the pins are carrying an address vs. data. ALE = 1 when the pins carry an address and 0 otherwise. ALE can be used to enable an external address latch that will hold the address value after it has been removed from the pins.

7. Programming P0 Using it as an output port: MOVA, #55H BACK:MOVP0, A ACALLDELAY CPLA SJMPBACK –This will continuously output 01010101 followed by 10101010 on P0 separated by a certain delay. –Port P0 is initialized as output by default, so no need to configure it. Using it as an input port: MOVA, #0FFH MOVP0, A BACK:MOVA, P0 MOVP1, A SJMPBACK –This will continuously read from port P0 and write the same value to port P1. –Port P0 is initialized as output by default, so it needs to be configured for input by writing 1’s to all of its bits.

8. Port P1 Can be used both for input and output. Its pins are connected to internal pull-up resistors so no external pull-up is needed. –Therefore, if the external pin is left un-connected, the matching bit will be read as a logic high. Configured for output by default. –To configure it for input a 1 must be written into each bit.

9. All Input or All Output? Do these ports operate only as 8-bit input or 8-bit output ports? NO. –The individual bits of each port can be operated as either input or output. A pin is output by default. It can be made an input by writing 1 in its corresponding bit in the SFR register.

10. Dual Role of P1 Pins In the 8052, pins P1.0 and P1.1 serve a second function. –They are the external controls for timer T2. –Since there is no T2 in 8051 and 8031, these pins don’t have any special function in these chips.

11. Port P2 and its Dual Role P2 is very similar to P1 in its basic operation and in the fact that it does not need external pull-up. As it was shown for P0, P2 also serves as pins A8 – A15 (the upper 8 bits of he address bus) when accessing external memory. –The upper 8 bits of the address will be kept on the P2 pins for the duration of the memory cycle. No need for external latching.

12. Port P3 P3 is similar to P1 and P2 in its basic operation and in the fact that it does not need external pull-up.

13. Functions of the P3 Pins All port P3 pins are multifunctional, they are not only I/O port pins but they also serve special functions. MSBLSB P3.7P3.6P3.5P3.4P3.3P3.2P3.1P3.0 RDWRT1T0INT1INT0TXDRCD P3.7Read SignalP3.3External Interrupt P3.6Write SignalP3.2External Interrupt P3.5Timer 1 external input P3.1Serial Output P3.4Timer 0 external input P3.0Serial Input

14. Read-Modify-Write Instructions All of the following instructions read the last value stored in the latch. ANLORL XRLJBC CPLINC DECDJNZ MOV PX.Y, CCLR PX.Y SETB PX.Y –All other instructions will read the value from the pin.

15. Driving Ability The pins of ports P1, P2, and P3 have a fan-out of 4 LS TTL inputs only. The fan-out of the pins of port P0 depends on the size of the external resistor used for the pull- up. –You should not expect a fan-out for P0 pins of more than 8 inputs.

16. Accessing External Memory As it has been noted before, the 8051 does not have an address or data bus. Instead, the pins of ports P0 and P2 are used for that purpose. –The pins of port P0 double as AD0 – AD7 (multiplexed). –The pins of port P2 double as A8 – A15. During a memory access (read from/write to external data memory or instruction fetch from external program memory): –The pins of port P0 first carry the lower 8-bits of the address, then switch operation to become the data bus. –The ALE signal is set to 1 during the period when the address is on the bus. –The pins of port P2 carry the upper 8-bits of the address through out the memory access cycle.

17. Accessing External Memory What about the values that were on the ports previously? –The values are stored in the latches in the SFR and are restored after the memory access operation. –The one exception is P0 where the value stored in the register is always over-written. This is due to the use of the P0 pins for the bidirectional data bus.

18. Accessing External Memory Access to external program memory always requires a 16-bit address. –Therefore, ports P0 and P2 are always used during external instruction fetch operations. Access to external data memory may use an 8-bit or 16-bit address depending on the instruction. MOVXA, @DPTR –Uses a 16-bit address. MOVXA, @R0 –Uses an 8-bit address. –However, using a value placed on P2 before the second MOVX instruction allows us to provide a 16-bit address if necessary.

19. The Read and Write Signals It has also been noted before that the 8051 has separate program and data memory spaces. –It therefore also has separate external signals for accessing the two different memories. The PSEN signal is used during read cycles from program memory. The RD and WR signals are used during read cycles from external data memory.

20. Example #7.1

22. Single-Bit Instructions

23. Example #7.2

24. Example #7.3

25. Example #7.4

26. Example #7.5

27. Example #7.6

28. Example #7.7

29. Example #7.8

30. Example #7.9

31. Example #7.10

32. Example #7.11

33. Example #7.12

34. Example #7.13

35. Example #7.14

36. Example #7.15

37. Carry-bit related Instruction

38. Swap Instruction

39. ASCII Code for 0-9

40. Example #7.16

41. Example #7.17