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8051 Core Specification. Outlines Introduction Introduction Architecture Architecture Operation Operation Registers Registers.

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Presentation on theme: "8051 Core Specification. Outlines Introduction Introduction Architecture Architecture Operation Operation Registers Registers."— Presentation transcript:

1 8051 Core Specification

2 Outlines Introduction Introduction Architecture Architecture Operation Operation Registers Registers

3 Introduction MCS-51 family, originally designed by Intel in the 1980 ’ s MCS-51 family, originally designed by Intel in the 1980 ’ s Used in a large percentage of embedded systems Used in a large percentage of embedded systems Includes several on-chip peripherals, like timers and counters Includes several on-chip peripherals, like timers and counters 128 bytes of on-chip data memory and up to 4K bytes of on-chip program memory 128 bytes of on-chip data memory and up to 4K bytes of on-chip program memory

4 Features (1/2) 8-bit CPU optimized for control applications 8-bit CPU optimized for control applications Extensive Boolean processing (single-bit logic) capabilities Extensive Boolean processing (single-bit logic) capabilities 64K Program Memory address space 64K Program Memory address space 64K Data Memory address space 64K Data Memory address space Up to 4K bytes of on-chip Program Memory Up to 4K bytes of on-chip Program Memory 128 bytes of on-chip Data RAM 128 bytes of on-chip Data RAM 32 bi-directional and individually addressable I/O lines 32 bi-directional and individually addressable I/O lines Two 16-bit timer/counters Two 16-bit timer/counters 6-source/5-vector interrupt structure with two priority levels 6-source/5-vector interrupt structure with two priority levels

5 Features (2/2)

6 Outlines Introduction Introduction Architecture Architecture Operation Operation Registers Registers

7 Architecture Memory Organization Memory Organization CPU Clock CPU Clock Interrupt Structure Interrupt Structure Port Structures Port Structures Timer/Counters Timer/Counters Reset Reset

8 Memory Organization (1/3) Logical separation of program and data memory Logical separation of program and data memory Separate address spaces for Program (ROM) and Data (RAM) Memory Separate address spaces for Program (ROM) and Data (RAM) Memory Allow Data Memory to be accessed by 8-bit addresses quickly and manipulated by 8-bit CPU Allow Data Memory to be accessed by 8-bit addresses quickly and manipulated by 8-bit CPU Program Memory Program Memory Only be read, not written to Only be read, not written to The address space is 16-bit, so maximum of 64K bytes The address space is 16-bit, so maximum of 64K bytes Up to 4K bytes can be on-chip (internal) of 8051 core Up to 4K bytes can be on-chip (internal) of 8051 core PSEN (Program Store Enable) is used for access to external Program Memory PSEN (Program Store Enable) is used for access to external Program Memory

9 Memory Organization (2/3) Data Memory Data Memory Includes 128 bytes of on-chip Data Memory which are more easily accessible directly by its instructions Includes 128 bytes of on-chip Data Memory which are more easily accessible directly by its instructions There is also a number of Special Function Registers (SFRs) There is also a number of Special Function Registers (SFRs) Internal Data Memory contains four banks of eight registers and a special 32-byte long segment which is bit addressable by 8051 bit-instructions Internal Data Memory contains four banks of eight registers and a special 32-byte long segment which is bit addressable by 8051 bit-instructions External memory of maximum 64K bytes is accessible by “ movx ” External memory of maximum 64K bytes is accessible by “ movx ”

10 Memory Organization (3/3) Internal Data Memory, 128 bytes Internal Data Memory, 128 bytes

11 CPU Clock 8051 microcontroller has a clock input pin 8051 microcontroller has a clock input pin

12 Interrupt Structure The 8051 provides 4 interrupt sources The 8051 provides 4 interrupt sources Two external interrupts Two external interrupts Two timer interrupts Two timer interrupts Additional description follows in Operations chapter Additional description follows in Operations chapter

13 Port Structures (1/3) The 8051 contains four I/O ports The 8051 contains four I/O ports All four ports are bidirectional All four ports are bidirectional Each port has SFR (Special Function Registers P0 through P3) which works like a latch, an output driver and an input buffer Each port has SFR (Special Function Registers P0 through P3) which works like a latch, an output driver and an input buffer Both output driver and input buffer of Port 0 and output driver of Port 2 are used for accessing external memory Both output driver and input buffer of Port 0 and output driver of Port 2 are used for accessing external memory

14 Port Structures (2/3) Accessing external memory works like this Accessing external memory works like this Port 0 outputs the low byte of external memory address (which is time-multiplexed with the byte being written or read) Port 0 outputs the low byte of external memory address (which is time-multiplexed with the byte being written or read) Port 2 outputs the high byte (only needed when the address is 16 bits wide) Port 2 outputs the high byte (only needed when the address is 16 bits wide)

15 Port Structures (3/3) Port 3 pins are multifunctional Port 3 pins are multifunctional The alternate functions are activated with the 1 written in the corresponding bit in the port SFR The alternate functions are activated with the 1 written in the corresponding bit in the port SFR

16 Read-Modify-Write Feature (1/2) When reading a port some instructions read the latch and others read the pin When reading a port some instructions read the latch and others read the pin The instructions that read the latch rather than the pin are the ones that read a value (possibly change it), an then rewrite it to the latch are called “ read-modify-write ” instructions The instructions that read the latch rather than the pin are the ones that read a value (possibly change it), an then rewrite it to the latch are called “ read-modify-write ” instructions

17 Read-Modify-Write Feature (2/2)

18 Timer/Counters The 8051 has two 16-bit Timer/Counter registers The 8051 has two 16-bit Timer/Counter registers Timer 0 Timer 0 Timer 1 Timer 1 Both can work either as timers or event counters Both can work either as timers or event counters Both have four different operating modes from which to select (all modes are described in Operations chapter) Both have four different operating modes from which to select (all modes are described in Operations chapter)

19 Reset The reset input is the RST pin The reset input is the RST pin

20 Outlines Introduction Introduction Architecture Architecture Operation Operation Registers Registers

21 Instruction Set Optimized for 8-bit control applications Optimized for 8-bit control applications Fast addressing modes for accessing internal RAM in order to facilitate byte operations on small data structures Fast addressing modes for accessing internal RAM in order to facilitate byte operations on small data structures Good for systems that require a lot of Boolean processing because of its extensive support for one-bit variables as a separate data type Good for systems that require a lot of Boolean processing because of its extensive support for one-bit variables as a separate data type

22 Addressing Modes (1/3) Direct Addressing Direct Addressing Operand is specified by an 8-bit address field in the instruction Operand is specified by an 8-bit address field in the instruction This address mode is possible only for addressing internal Data RAM and SFRs This address mode is possible only for addressing internal Data RAM and SFRs Indirect Addressing Indirect Addressing The instruction specifies a register which contains the address of the operand The instruction specifies a register which contains the address of the operand The address register for 8-bit addresses can be R0 or R1 of the selected bank, or the Stack Pointer The address register for 8-bit addresses can be R0 or R1 of the selected bank, or the Stack Pointer The address register for 16-bit addresses can only be 16-bit “ data pointer ” register, DPTR The address register for 16-bit addresses can only be 16-bit “ data pointer ” register, DPTR Both internal and external RAM can be indirectly addressed Both internal and external RAM can be indirectly addressed

23 Addressing Modes (2/3) Register Instructions Register Instructions Special instructions are used for accessing four register banks (containing R0 to R7) Special instructions are used for accessing four register banks (containing R0 to R7) This instructions have 3-bit register specification within the opcode This instructions have 3-bit register specification within the opcode This way of accessing registers is much more efficient because of no need for the address byte This way of accessing registers is much more efficient because of no need for the address byte When such instruction is executed one of registers in selected ban is accessed When such instruction is executed one of registers in selected ban is accessed Register bank is selected by two bank select bits in PSW Register bank is selected by two bank select bits in PSW

24 Addressing Modes (3/3) Register-Specific Instructions Register-Specific Instructions These are instructions which are specific to a certain register and they don ’ t need an address byte (they always operate with the same register) These are instructions which are specific to a certain register and they don ’ t need an address byte (they always operate with the same register) Immediate Constants Immediate Constants The value of a constant follows the opcode The value of a constant follows the opcode MOV A, #10 – loads the Accumulator with the decimal number 10 MOV A, #10 – loads the Accumulator with the decimal number 10 Indexed Addressing Indexed Addressing Only Program Memory can be accessed and it can be a read Only Program Memory can be accessed and it can be a read Used for reading look-up tables in Program Memory and “ case jump ” instruction Used for reading look-up tables in Program Memory and “ case jump ” instruction

25 Instruction Types of 8051 Arithmetic Instructions Arithmetic Instructions Logical Instructions Logical Instructions Data Transfers Data Transfers Lookup Tables Lookup Tables Boolean Instructions Boolean Instructions Jump Instructions Jump Instructions

26 Arithmetic Instructions

27 Logical Instructions

28 Data Transfers

29 Lookup Tables

30 Boolean Instructions

31 Jump Instructions

32 Timer/Counters 8051 has two 16-bit Timer/Counter registers 8051 has two 16-bit Timer/Counter registers Timer/Counter 0 Timer/Counter 0 Timer/Counter 1 Timer/Counter 1 These registers can be used as timers or as event counters These registers can be used as timers or as event counters When a register is in “ Timer ” state, it is incremented every machine cycle When a register is in “ Timer ” state, it is incremented every machine cycle In “ Counter ” state, the register is incremented when there is a 1-to-0 transition at its external input pin, pin T0 or T1 In “ Counter ” state, the register is incremented when there is a 1-to-0 transition at its external input pin, pin T0 or T1 Both registers have additional four operating modes Both registers have additional four operating modes

33 Timer/Counter Modes The selection for “ Timer ” or “ Counter ” is done by control bits C/T in the TMOD register The selection for “ Timer ” or “ Counter ” is done by control bits C/T in the TMOD register Both Timer/Counters have four operating modes, which Modes 0, 1 and 2 are the same for both Timer/Counters, Mode 3 is different Both Timer/Counters have four operating modes, which Modes 0, 1 and 2 are the same for both Timer/Counters, Mode 3 is different Modes are selected by bit pairs (M1, M0) in TMOD SFR Modes are selected by bit pairs (M1, M0) in TMOD SFR Another SFR used for work with Timer/Counters is TCON containing flag (TFx) and control (TRx) bits Another SFR used for work with Timer/Counters is TCON containing flag (TFx) and control (TRx) bits

34 Mode 0 Both Timer 1 and Timer 0 in Mode 0 operate as an 8-bit Counters (with a divide-by-32 prescaler) Both Timer 1 and Timer 0 in Mode 0 operate as an 8-bit Counters (with a divide-by-32 prescaler) Timer register is configured as a 13-bit register consisting of all 8 bits of TH1 and the lower 5 bits of TL1 Timer register is configured as a 13-bit register consisting of all 8 bits of TH1 and the lower 5 bits of TL1 The upper 3 bits of TL1 are indeterminate and should be ignored The upper 3 bits of TL1 are indeterminate and should be ignored Setting the run flag (TR1) does not clear the register Setting the run flag (TR1) does not clear the register Timer interrupt flag TF1 is set when the count rolls over from all 1s to all 0s Timer interrupt flag TF1 is set when the count rolls over from all 1s to all 0s Mode 0 operation is the same for Timer 0 as for Timer 1. Just substitute Timer 0 for the corresponding Timer 1 signals Mode 0 operation is the same for Timer 0 as for Timer 1. Just substitute Timer 0 for the corresponding Timer 1 signals

35 Mode 1 Mode 1 is the same as Mode (for both Timers), except that the Timer register is configured as 16-bit register Mode 1 is the same as Mode (for both Timers), except that the Timer register is configured as 16-bit register

36 Mode 2 Both Timer registers are configured as an 8-bit Counters (TL1 and TL0) with automatic reload Both Timer registers are configured as an 8-bit Counters (TL1 and TL0) with automatic reload Overflow from TL1 (TL0) sets TF1 (TF0) and also reloads TL1 (TL0) with the contents of Th1 (TH0), which is preset by software Overflow from TL1 (TL0) sets TF1 (TF0) and also reloads TL1 (TL0) with the contents of Th1 (TH0), which is preset by software The reload leaves TH1 (TH0) unchanged The reload leaves TH1 (TH0) unchanged

37 Mode 3 Mode 3 is different for Timer 1 and Timer 0 Mode 3 is different for Timer 1 and Timer 0 Timer 1 just holds its count. It operates the same as when TR1 is set to 0 Timer 1 just holds its count. It operates the same as when TR1 is set to 0 For Timer 0 is different, TL0 and TH0 of Timer 0 are established as two separate counters For Timer 0 is different, TL0 and TH0 of Timer 0 are established as two separate counters TL0 uses Timer 0 control bits for its work: C/T, GATE, TR0, ~INT0, and TF0 TL0 uses Timer 0 control bits for its work: C/T, GATE, TR0, ~INT0, and TF0 TH0 is locked into a timer function (counting machine cycles) and takes over the use of TR1 and TF1 from Timer 1. TH0 is now actually in control of “ Timer 1 ” interrupt TH0 is locked into a timer function (counting machine cycles) and takes over the use of TR1 and TF1 from Timer 1. TH0 is now actually in control of “ Timer 1 ” interrupt Mode 3 is provided for applications that require an extra 8-bit timer or counter Mode 3 is provided for applications that require an extra 8-bit timer or counter With Timer 0, 8051 looks like it has three Timer/Counters With Timer 0, 8051 looks like it has three Timer/Counters When Timer 0 in Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3, or can still be used in any application not requiring an interrupt When Timer 0 in Mode 3, Timer 1 can be turned on and off by switching it out of and into its own Mode 3, or can still be used in any application not requiring an interrupt

38 Interrupt (1/3) 8051 provides 4 interrupt sources 8051 provides 4 interrupt sources 2 external interrupts 2 external interrupts 2 timer interrupts 2 timer interrupts They are controlled via two SFRs, IE and IP They are controlled via two SFRs, IE and IP Each interrupt source can be individually enabled or disabled by setting or clearing a bit in IE (Interrupt Enable). IE also exists a global disable bit, which can be cleared to disable all interrupts at once Each interrupt source can be individually enabled or disabled by setting or clearing a bit in IE (Interrupt Enable). IE also exists a global disable bit, which can be cleared to disable all interrupts at once

39 Interrupt (2/3) Each interrupt source can also be individually set to one of two priority levels by setting or clearing a bit in IP (Interrupt Priority) Each interrupt source can also be individually set to one of two priority levels by setting or clearing a bit in IP (Interrupt Priority) A low-priority interrupt can be interrupted by high- priority interrupt, but not by another low-priority one A low-priority interrupt can be interrupted by high- priority interrupt, but not by another low-priority one A high-priority interrupt can ’ t be interrupted by any other interrupt source A high-priority interrupt can ’ t be interrupted by any other interrupt source If interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced, so within each priority lever there is a second priority structure If interrupt requests of the same priority level are received simultaneously, an internal polling sequence determines which request is serviced, so within each priority lever there is a second priority structure

40 Interrupt (3/3) This internal priority structure is determined by the polling sequence, shown in the following table This internal priority structure is determined by the polling sequence, shown in the following table

41 External Interrupts External interrupts ~INT0 and ~INT1 have two ways of activation External interrupts ~INT0 and ~INT1 have two ways of activation Level-activated Level-activated Transition-activated Transition-activated This depends on bits IT0 and IT1 in TCON This depends on bits IT0 and IT1 in TCON The flags that actually generate these interrupts are bits IE0 and IE1 in TCON The flags that actually generate these interrupts are bits IE0 and IE1 in TCON On-chip hardware clears that flag that generated an external interrupt when the service routine is vectored to, but only if the interrupt was transition-activated On-chip hardware clears that flag that generated an external interrupt when the service routine is vectored to, but only if the interrupt was transition-activated When the interrupt is level-activated, then the external requesting source is controlling the request flag, not the on-chip hardware When the interrupt is level-activated, then the external requesting source is controlling the request flag, not the on-chip hardware

42 Timer 0 and Timer 1 Interrupts Timer interrupts are generated by TF0 and TF1 flags in their respective Timer/Counter registers Timer interrupts are generated by TF0 and TF1 flags in their respective Timer/Counter registers Similarly like in the case of transition-activated external interrupts, the flag that generated an interrupt is cleared by the on-chip hardware when the service routine is vectored to Similarly like in the case of transition-activated external interrupts, the flag that generated an interrupt is cleared by the on-chip hardware when the service routine is vectored to

43 Handling of Interrupts (1/5) When interrupt occurs (or correctly, when the flag for an enabled interrupt is found to be set (1)), the interrupt system generates an LCALL to the appropriate location in Program Memory, unless some other conditions block the interrupt When interrupt occurs (or correctly, when the flag for an enabled interrupt is found to be set (1)), the interrupt system generates an LCALL to the appropriate location in Program Memory, unless some other conditions block the interrupt Several conditions can block an interrupt Several conditions can block an interrupt An interrupt of equal or higher priority level is already in progress An interrupt of equal or higher priority level is already in progress The current (polling) cycle is not the final cycle in the execution of the instruction in progress The current (polling) cycle is not the final cycle in the execution of the instruction in progress The instruction in progress is RETI or any write to IE or IP registers The instruction in progress is RETI or any write to IE or IP registers

44 Handling of Interrupts (2/5) If an interrupt flag is active but not being responded to for one of the above conditions, must be still active when the blocking condition is removed, or the denied interrupt will not be serviced If an interrupt flag is active but not being responded to for one of the above conditions, must be still active when the blocking condition is removed, or the denied interrupt will not be serviced Next step is saving the registers on stack. The hardware-generated LCALL causes only the contents of the Program Counter to be pushed onto the stack, and reloads the PC with the beginning address of the service routine Next step is saving the registers on stack. The hardware-generated LCALL causes only the contents of the Program Counter to be pushed onto the stack, and reloads the PC with the beginning address of the service routine In some cases it also clears the flag that generated the interrupt, and in other cases it doesn ’ t. It clears an external interrupt flag (IE0 or IE1) only if it was transition-avtivated. In some cases it also clears the flag that generated the interrupt, and in other cases it doesn ’ t. It clears an external interrupt flag (IE0 or IE1) only if it was transition-avtivated.

45 Handling of Interrupts (3/5) Having only PC be automatically saved gives programmer more freedom to decide how much time to spend saving other registers. Programmer must also be more careful with proper selection, which register to save Having only PC be automatically saved gives programmer more freedom to decide how much time to spend saving other registers. Programmer must also be more careful with proper selection, which register to save The service routine for each interrupt begins at a fixed location. The interrupt locations are spaced at 8-byte interval, beginning at 0003H for External Interrupt 0, 000BH for Timer 0, 0013H for External Interrupt 1 and 001BH for Timer 1, shown in the following tables The service routine for each interrupt begins at a fixed location. The interrupt locations are spaced at 8-byte interval, beginning at 0003H for External Interrupt 0, 000BH for Timer 0, 0013H for External Interrupt 1 and 001BH for Timer 1, shown in the following tables

46 Handling of Interrupts (4/5)

47 Handling of Interrupts (5/5) Execution of service routine continues from that location until the end, that is until it encounters RETI. Execution of service routine continues from that location until the end, that is until it encounters RETI. RETI instruction does two things RETI instruction does two things It informs the processor that this interrupt routine is finished It informs the processor that this interrupt routine is finished Secondly, reloads the PC from the top bytes from the stack Secondly, reloads the PC from the top bytes from the stack Similar result could be accomplished with RET, with the distinction that the interrupt control system would be thinking an interrupt was still in progress Similar result could be accomplished with RET, with the distinction that the interrupt control system would be thinking an interrupt was still in progress

48 Reset The reset input is RST pin The reset input is RST pin To accomplish a reset the RST pin must be held high for at least two machine cycles To accomplish a reset the RST pin must be held high for at least two machine cycles In the response on the RST signal, CPU generates an internal reset In the response on the RST signal, CPU generates an internal reset The external reset signal is asynchronous to the internal clock The external reset signal is asynchronous to the internal clock In the internal reset algorithm, 0s are written to all the SFRs except the port latches and Stack Pointer In the internal reset algorithm, 0s are written to all the SFRs except the port latches and Stack Pointer The port latches are initialized to FFH and Stack Pointer to 07H The port latches are initialized to FFH and Stack Pointer to 07H Driving ALE and PSEN pins to 0 while reset is active could cause the device to go into an indeterminate state Driving ALE and PSEN pins to 0 while reset is active could cause the device to go into an indeterminate state The internal RAM is not affected by reset. On power up the RAM content is indeterminate The internal RAM is not affected by reset. On power up the RAM content is indeterminate

49 Outlines Introduction Introduction Architecture Architecture Operation Operation Registers Registers

50 8051 Registers

51 PSW: Program Status Word (bit addressable) The PSW register contains several status bits that reflect the current state of the CPU The PSW register contains several status bits that reflect the current state of the CPU

52 IE: Interrupt Enable Register (bit addressable) If the bit is 0, the corresponding interrupt is disabled. Otherwise, the interrupt is enabled. If the bit is 0, the corresponding interrupt is disabled. Otherwise, the interrupt is enabled.

53 IP: Interrupt Priority Register (bit addressable) If the bit is 0, the corresponding interrupt has a lower priority and if the bit is 1, the interrupt has a higher priority If the bit is 0, the corresponding interrupt has a lower priority and if the bit is 1, the interrupt has a higher priority

54 TCON: Timer/Counter Control Register (bit addressable)

55 TMOD: Timer/Counter Mode Control Register (not bit addressable)


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