Presentation on theme: "SYSTEM CLOCK Clock (CLK) : input signal which synchronize the internal and external operations of the microprocessor."— Presentation transcript:
SYSTEM CLOCK Clock (CLK) : input signal which synchronize the internal and external operations of the microprocessor.
The clock source is generated by 8284 ( clock generator and Driver IC ) CLK ( 8) of 8284 is connected to pin / also supplies it with 2 of it's control lines – RESET and READY. The RESET signal does resets the This line can also be used by other peripherals on the computer so that they reset when the 8088 resets. READY used to slow down the 8088 ; Dfrom IO circuit thru RD1 and RD2 A crystal oscillator is connected between X1 and X2 which provides a FUNDAMENTAL CRYSTAL FREQUENCY. ( FCF) 33% duty cycle the FCF is divided by 3 internally by 8244 to provide the necessary CLK output pin pclk provide 50% of duty cycle to drive periperal devices CLOCK GENERATOR IC
A bus cycle defines the basic operation that a microprocessor performs to communicate with external devices. Examples of bus cycle are memory read, memory write, input/output read and input/output write. A bus cycle corresponds to a sequence of events that starts with an address being output on the system bus followed by a read or write data transfer. During these operations, a series of control signal are also produced by the MPU to control the direction and timing of the bus. Each bus cycle consists of at least four clock periods, T1, T2, T3 and T4. These clock period are also called T-state. These 4 clock states gives a bus cycle duration of ( 125 ns * 4 ) = 500 ns in a 8-Mhz 8088 Idle State: no bus activity ; one clock period Wait state : controlled by READY signal ; inserted between T3 and T4 when READY = 0. Bus cycle will complete when READY = 1 BUS CYCLE AND TIME STATES
Bus Cycle and Time States T1 - start of bus cycle. Actions include setting control signals to give the required values for ALE, DTR, IO/M putting a valid address onto the address bus. T2 - the RD or WR control signals are issued, DEN is asserted and in the case of a write, data is put onto the data bus. The DEN turns on the data bus buffers to connect the CPU to the external data bus. The READY input to the CPU is sampled at the end of T2 and if READY is low, a wait state TW (one or more) is inserted before T3 begins. T3 - this clock period is provided to allow memory to access the data. If the bus cycle is a read cycle, the data bus is sampled at the end of T3. T4 - all bus signals are deactivated in preparation for the next clock cycle. The 8088 also finishes sampling the data (in a read cycle) in this period. For the write cycle, the trailing edge of the WR signal transfers data to the memory or I/O, which activates and write when WR returns to logic 1 level.
4-5 System Timing Diagrams T-State: — One clock period is referred to as a T-State T-State — An operation takes an integer number of T-States CPU Bus Cycle: — A bus cycle consists of 4 or more T-States T1T2T3T4
4-6 Dump address on address bus. Issue a read ( RD ) and set M/ IO to 1. Wait for memory access cycle. Memory Read Timing Diagrams
4-7 Memory Read Timing Diagrams T1 T2 T3T4 CLK ALE A[19:16] S3-S6 A[15:8] AD[7:0]A[7:0]D[7:0] IO/M DT/R DEN RD WR A[15:8 ] AD[7:0] A[15:0] Buffer D latch Trans -ceiver D[7:0] DT/R DEN IO/M WR RD 8088 Memory
4-8 Dump address on address bus. Dump data on data bus. Issue a write ( WR ) and set M/ IO to 1. Memory Write Timing Diagrams
4-9 Memory Write Timing Diagrams T1 T2 T3T4 CLK ALE A[19:16] S3-S6 A[15:8] AD[7:0]A[7:0]D[7:0] IO/M DT/R DEN RD WR A[15:8 ] AD[7:0] A[15:0] Buffer D latch Trans -ceiver D[7:0] DT/R DEN IO/M WR RD 8088 Memory
4-10 Bus Timing During T 1 : The address is placed on the Address/Data bus. Control signals M/ IO, ALE and DT/ R specify memory or I/O, latch the address onto the address bus and set the direction of data transfer on data bus. During T 2 : 8086 issues the RD or WR signal, DEN, and, for a write, the data. DEN enables the memory or I/O device to receive the data for writes and the 8086 to receive the data for reads. During T 3 : This cycle is provided to allow memory to access data. READY is sampled at the end of T 2. If low, T 3 becomes a wait state. Otherwise, the data bus is sampled at the end of T 3. During T 4 : All bus signals are deactivated, in preparation for next bus cycle. Data is sampled for reads, writes occur for writes.
4-11 Setup & Hold Time Setup time – The time before the rising edge of the clock, while the data must be valid and constant Hold time – The time after the rising edge of the clock during which the data must remain valid and constant
4-12 Bus Timing Diagram
4-13 Bus Timing Timing: –Each BUS CYCLE on the 8086 equals four system clocking periods (T states). –The clock rate is 5MHz, therefore one Bus Cycle is 800ns. –The transfer rate is 1.25MHz. Memory specs (memory access time) must match constraints of system timing. For example, bus timing for a read operation shows almost 600ns are needed to read data. However, memory must access faster due to setup times, e.g. Address setup and data setup. This subtracts off about 150ns. Therefore, memory must access in at least 450ns minus another 30-40ns guard band for buffers and decoders. 420ns DRAM required for the 8086.
10.6 System Time Diagrams - CPU Bus Cycle T2T2 T3T3 TWTW T4T4 Read Cycle (instruction fetch and memory operand read) A 8 - A 15 Address latches store the actual values Memory Cycle (I/O cycle is similar but IO/M = 1) S 3 - S 6 Tri-state A 16 -A 19 A 0 - A 7 T1T1 CLK ALE IO/M A 16 - A 19 A 8 - A 15 RD AD 0 - AD 7 DT/R READY DEN Direction “READ” for the Data BufferEnables Data Buffer WR AD 0 - AD 7 DT/R Write Cycle (memory operand write) A 0 - A 7 D 0 - D 7 (Data out) DEN Direction “READ” for the Data Buffer Enables Data Buffer Memory reads Data Bus The slow device drives READY= 0 the P samples READY (if 0 a WAIT state follows) D 0 - D 7 (Data in) P reads Data Bus