1. Lecture 21: Registers and Counters (1)
CPE 201 Digital Design
Lecture 21:
Registers and Counters (1)

2. Lecture Outline
Registers

3. Registers – Introduction
So far we introduced increasingly complex digital building blocks
Gates, multiplexers, decoders, basic registers, and controllers
Controllers are good for systems with control inputs/outputs
Control input: Single bit (or just a few), representing environment event
e.g., 1 bit representing button pressed
Data input: Multiple bits collectively representing single entity
e.g., 7 bits representing temperature in binary

4. Registers – Introduction
Need building blocks for data
Datapath components, aka register-transfer-level (RTL) components, store/transform data
Put datapath components together to form a datapath
We will introduce several datapath components, and simple datapaths
Register: A group of flip-flops each storing one bit of information
Registers include flip-flops and gates: flip-flops hold the information, gates control how the information is transferred to the register
Counter is a register that goes through a predetermined sequence of states

5. Registers load Basic register loads on every clock cycle
Can store data, very common in datapaths
Basic register: loaded every cycle
Useful for implementing FSM, stores encoded state
For other uses, may want to load only on certain cycles
Combinational
logic
State register s1 s0 n1 n0 x b
clk
load D Q I 2 3 Q2 Q3 Q1 Q0 1
clk
4-bit register
Basic register loads on every clock cycle
How to extend to only load on certain cycles?

6. Register with Parallel Load1 1
To fully synchronize the system, clock signals should arrive at the same time at all flip-flops.
Therefore we should not control the clock by gates. I0 I3 I2 I1 1
Load = 1, we load data
Load =0, register content does not change

7. Register with Parallel Load
Load =0, register content does not change 1 A0 A3 A2 A1

8. Register with Parallel Load
Add 2x1 mux to front of each flip-flop
Register’s load input selects mux input to pass
Either existing flip-flop value, or new value to load

9. Basic Example Using RegistersQ3 Q2 Q1 Q0 a3 a2 a1 a0 I 3 2 1 ld R1 R0 R2
clk
Parallel transfer
This example will show how registers load simultaneously on clock cycles
Notice that all load inputs set to 1 in this example - just for demonstration purposes

10. Basic Example Using RegistersQ3 Q2 Q1 Q0 a3 a2 a1 a0 I 3 2 1 ld R1 R0 R2
clk

11. Register Example using the Load Input: Weight Sampler
Scale has two displays
Present weight
Saved weight
Useful to compare present item with previous item
Use register to store weight
Pressing button causes present weight to be stored in register
Register contents always displayed as “Saved weight,” even when new present weight appears
Scale
Weight Sampler 1 1 1
Save b I 3 I 2 I 1 I
3 pounds
2 pounds
load 1
Present weight
clk Q3 Q2 Q1 Q0
3 pounds
Saved weight

12. Register Example: Above-Mirror Display
32 wires 8
Shorthand notation C
Loaded on clock edge 8 d0
load r
eg0 T i0 2 × 4 8 1 1
8-bit
Earlier example: Four simultaneous values from car’s computer
To reduce wires:
computer writes only 1 value at a time, loads into one of four registers
Was: = 32 wires
Now: = 11 wires d1
load r
eg1 A a0 4 × 1 i0 i1 i1 8 a1 d D d2
load r
eg2 I 8 i2 8 d3
load r
eg3 M e 1
load i3 s1 s0 8 x y

13. Shift Register Shift right A: 1001 (original) 0100 0010 0001 0000
Move each bit one position right
Shift in 0 to leftmost bit
Register contents
before shift right
Register contents
after shift right
E.g.: Do four right shifts on 1001, showing value after each shift
shr_in
Implementation: Connect flip-flop output to next flip-flop’s input A:
1001 (original)
0100
0010
0001
0000

14. Shift Register To allow register to either shift or maintain value
Control input shr: 0 means maintain value, 1 shift
Input shr_in: value to shift in
May be 0, or 1
Use 2x1 muxes
Note: Can easily design shift register that shifts left instead

15. Rotate Register
Register contents
before rotate right
after rotate right
Rotate right: Like shift right, but leftmost bit comes from rightmost bit

16. Shift Register Example: Above-Mirror Display
Earlier example: = 11 wires from car’s computer to above-mirror display’s four registers
Better than 32 wires, but 11 still a lot – want fewer for smaller wire bundles
Use shift registers
Wires: 1+2+1=4
Computer sends one value at a time, one bit per clock cycle
11 wires c d0 d1 d2 d3 e i0 s1 s0 x y i1 i2 i3 a0 a1
shi f t 2 × 4 8 D d 1
shr
shr_in r
eg0
eg1
eg2
eg3 T A I M
Note: this line is 1 bit, rather than 8 bits like before

17. Multifunction (Universal) Registers
Many registers have multiple functions
Load, shift, clear (load all 0s)
And retain present value, of course
Easily designed using muxes
Just connect each mux input to achieve desired function s1 s0
Operation
Maintain present value 1
Parallel load 1
Shift right 1 1
Shift left

18. Multifunction Registers with Separate Control Inputs
Maintain present value
Shift left
Shift right
Shift right – shr has priority over shl
Parallel load
Parallel load – ld has priority
Operation
shl
shr ld 1 Q2 Q1 Q0 Q3 I 2 1 3 s1
shr_in
shr
shl ld s0
shl_in c
ombi- n a
tional ci r
cuit ?
Maintain value
Shift left
Shift right
Parallel load
Note
Operation s0 s1 1
Outputs
Inputs ld
shr
shl
Truth table for combinational circuit
s1 = ld’*shr’*shl + ld’*shr*shl’ + ld’*shr*shl
s0 = ld’*shr’*shl + ld

19. Register Operation Table
Register operations typically shown using compact version of table
X means same operation whether value is 0 or 1
One X expands to two rows
Two Xs expand to four rows
Put highest priority control input on left to make reduced table simple
Inputs
Outputs No t e ld
shr
shl s1 s0
Operation ld
shr
shl
Ope r a
tion
Maintain value M ai n
tain v
alue 1 1 1
Shift left 1
Shi f
t le f t
Shift right 1
Shift right X 1
Parallel load X 1
Parallel load 1

20. Register Design Process
Can design register with desired operations using simple four-step process

21. Register Design Example
Operation
Maintain present value
Parallel load
Shift left
Synchronous clear
Synchronous set s0 1 s1 s2
Desired register operations
Synchronous clear, synchronous set, load, shift left
Step 1: Determine mux size D Q Qn 7 6 3 2 1 Id 5 4 s2 s1 s0
from
Qn-1
5 operations: above, plus maintain present value (don’t forget this one!)  Use 8x1 mux
Step 2: Create mux operation table
Step 3: Connect mux inputs
Step 4: Map control lines
Operation
Maintain present value
Shift left
Parallel load
Set to all 1s
Clear to all 0s s0 1 s1 s2
shl X ld
clr
Inputs
Outputs
set
s2 = clr’*set
s1 = clr’*set’*ld’*shl + clr
s0 = clr’*set’*ld + clr

22. Register Design Example3 I 2 I 1 I I 3 I 2 I 1 I
shl s2 s1
shl_in ld
combi-
shl_in s0
national
set
circuit Q3 Q2 Q1 Q0
clr Q3 Q2 Q1 Q0
Step 4: Map control lines
Operation
Maintain present value
Shift left
Parallel load
Set to all 1s
Clear to all 0s s0 1 s1 s2
shl X ld
clr
Inputs
Outputs
set
s2 = clr’*set
s1 = clr’*set’*ld’*shl + clr
s0 = clr’*set’*ld + clr

23. Serial Transfer
A digital system is in the serial mode when information is processed one bit at a time
Serial transfer of information from A to B

24. Remember 4-bit Parallel Adder Circuit?
For small digital circuits, serial addition requires less equipment
4-bit parallel adder

25. Serial Addition
Slower compared to parallel addition, but uses less equipment
Use shift registers
A, B hold data
Use a full adder
Carry out stored in
a D flip-flop
PA uses more FAs
compared to SA
PA is a combinational circuit, SA is sequential
Which register holds the sum?

26. Serial Adder using Design Procedure
Present State Inputs Next State Output Flip-Flop inputs
Q (carry) x y Q (carry) S J K0
J0=xy
K0=x’y’= (x+y)’
S=x  y  Q x x x x x x x x

27. Serial 4-bit Parallel Adder Circuit

28. Readings
Chapter 6
Sections 6.1 – 6.2