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Chapter 1 — Computer Abstractions and Technology — 1 Lecture 7 Carry look ahead adders, Latches, Flip-flops, registers, multiplexors, decoders Digital Works intro PH 3 : Appendix B.6-9

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Chapter 1 — Computer Abstractions and Technology — 2 Adders Last time we developed a 32 bit ripple adder. It is not an efficient adder, although simple to understand, so how can we improve its performance. We will try to see what can be done to speed it up.

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— 3 Is a 32-bit ALU as fast as a 1-bit ALU? Is there more than one way to do addition? two extremes: ripple carry and sum-of-products Can you see the ripple? How could you get rid of it? c 1 = b 0 c 0 + a 0 c 0 + a 0 b 0 c 1 = (b 0 + a 0 )c 0 + a 0 b 0 c 2 = b 1 c 1 + a 1 c 1 + a 1 b 1 c 2 = (b 1 + a 1 )c 1 + a 1 b 1 c 3 = b 2 c 2 + a 2 c 2 + a 2 b 2 c 3 = … c 4 = b 3 c 3 + a 3 c 3 + a 3 b 3 c 4 = … Problem: ripple carry adder is slow

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— 4 An approach in-between our two extremes Motivation: If we didn't know the value of carry-in, what could we do? Let g i = a i b i, called generate, and, p i = a i + b i, called propagate. Now the equations can be written as below c 1 = g 0 + p 0 c 0 c 2 = g 1 + p 1 c 1 = g 1 + p 1 (g 0 + p 0 c 0 ) c 3 = g 2 + p 2 c 2 = g 2 + p 2 (g 1 + p 1 (g 0 + p 0 c 0 )) c 4 = g 3 + p 3 c 3 =... So we see it is possible to generate however many carries we desire that are independent of all carries except c 0. However it tends to become quite expensive in terms of numbers of gates. So what can we do? Carry-lookahead adder

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Chapter 1 — Computer Abstractions and Technology — 5 A four bit carry lookahead adder

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Chapter 1 — Computer Abstractions and Technology — 6 Cascade connection of 4-bit carry lookahead adders. Can’t build a 16 bit adder this way... (too big) Could use ripple carry of 4-bit CLA adders Better: use the CLA principle again!

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Chapter 1 — Computer Abstractions and Technology — 7 Memory Simple Flip-Flop Applications

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Chapter 1 — Computer Abstractions and Technology — 8 Basic bistable element.

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Chapter 1 — Computer Abstractions and Technology — 9 SR (set-reset) latch. (a) Logic diagrams. (b) Function table where Q + denotes the output Q in response to the inputs. (c) Two logic symbols.

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Chapter 1 — Computer Abstractions and Technology — 10 An application of the SR latch. (a) Effects of contact bounce. (b) A switch debouncer.

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Chapter 1 — Computer Abstractions and Technology — 11 latch. (a) Logic diagrams. (b) Function table where Q + denotes the output Q in response to the inputs. (c) Two logic symbols.

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Chapter 1 — Computer Abstractions and Technology — 12 Gated SR latch. (a) Logic diagram. (b) Function table where Q + denotes the output Q in response to the inputs. (c) Two logic symbols (c)(c)

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Chapter 1 — Computer Abstractions and Technology — 13 Gated D latch. (a) Logic diagram. (b) Function table where Q + denotes the output Q in response to the inputs. (c) Two logic symbols.

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Chapter 1 — Computer Abstractions and Technology — 14 Timing diagram for an SR latch.

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Chapter 1 — Computer Abstractions and Technology — 15 Timing diagram for a gated D latch.

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Chapter 1 — Computer Abstractions and Technology — 16 Positive-edge-triggered D flip-flop. (a) Logic diagram. (b) Function table where Q + denotes the output Q in response to the inputs. (c) Two logic symbols.

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Chapter 1 — Computer Abstractions and Technology — 17 Positive-edge-triggered D flip-flop NAND gates 5 and 6 serve as an latch. Thus as long as S = R = 0, i.e. S’ = R’ = 1, the state of the latch cannot change; while whenever S or R is 1, i.e. S’ or R’ is 0, but not both the latch sets or resets. Now if C = 0 the outputs of gates 2 and 3 are 1, regardless of D, so the latch does not change. Now assume D = 0. then the output at gate 4 is 1 and at gate 1 is 0 since the outputs at gates 4 and 2 are 1. When C goes from 0 to 1, the positive edge, all inputs to gate 3 become 1 so R’ = 0. But S’ remains 1 since the input from gate 1 is still 0 so Q = 0 and Q’ = 1. In addition the ouput 0 from gate 3 feeds back to gate 4 to keep the output there at 1 regardless of changes to D so long as C stays equal 1.

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Chapter 1 — Computer Abstractions and Technology — 18 Positive-edge-triggered flip-flop continued Now suppose C = 0 and D = 1. As before the ouputs from gates 2 and 3 are 1 causing the S’R’ latch to hold its current state. However D = 1 causes the output of gate 4 to be 0 which causes the output of gate 1 to be 1. Now when C changes to 1 both inputs to gate 2 become 1 so S’ = 0. R’ remains 1 since the input from gate 4 to gate 3 is 0. Now S’ = 0 and R’ = 1 causes Q = 1 and Q’ = 0. The 0 output from gate 2 causes the outputs at gates 1 and 3 to remain at 1. Thus if D changes as long as C = 1, there will be no change in the S’R’ latch.

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Chapter 1 — Computer Abstractions and Technology — 19 Timing diagram for a positive-edge-triggered D flip-flop.

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Chapter 1 — Computer Abstractions and Technology — 20 General model of a sequential network.

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Chapter 1 — Computer Abstractions and Technology — 21 Logic Design Basics Information encoded in binary Low voltage = 0, High voltage = 1 One wire per bit Multi-bit data encoded on multi-wire buses Combinational element Operate on data Output is a function of input State (sequential) elements Store information

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Chapter 1 — Computer Abstractions and Technology — 22 Combinational Elements AND-gate Y = A & B A B Y I0 I1 Y MuxMux S Multiplexer Y = S ? I1 : I0 A B Y + A B Y ALU F Adder Y = A + B Arithmetic/Logic Unit Y = F(A, B)

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Chapter 1 — Computer Abstractions and Technology — 23 Structure of a clocked synchronous sequential network.

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Chapter 1 — Computer Abstractions and Technology — 24 An m-bit register using D flip-flops

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Chapter 1 — Computer Abstractions and Technology — 25 Register File: Built using flip-flops

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Chapter 1 — Computer Abstractions and Technology — 26 Universal shift register. (a) Logic diagram. (b) Mode control. (c) Symbol.

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— 27 Do you understand? What is the “Mux”?

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Chapter 1 — Computer Abstractions and Technology — 28 Multiplexor A multiplexor that chooses one of two words. Built by using 1 bit multiplexors and stringing them together as on the right.

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Chapter 1 — Computer Abstractions and Technology — 29 An n-to-2 n -line decoder symbol.

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Chapter 1 — Computer Abstractions and Technology — 30 A 3-to-8-line decoder. (a) Logic diagram. (b) Truth table. (c) Symbol.

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— 31 Register File (Note: we still use the real clock to determine when to write)

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— 32 Simple Implementation The functional units we need for each instruction

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Chapter 1 — Computer Abstractions and Technology — 33 Simple implementation continued. Functions needed for loads and stores

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Chapter 1 — Computer Abstractions and Technology — 34 Simple implementation continued. What happens to the instruction

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Chapter 1 — Computer Abstractions and Technology — 35 Introduction to Digital Works

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Chapter 1 — Computer Abstractions and Technology — 36 The Digital Works Window

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Chapter 1 — Computer Abstractions and Technology — 37 Creating and using Macros Converting the two-input multiplexer circuit into a black box

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Chapter 1 — Computer Abstractions and Technology — 38 Creating the black box Left click on the arrow. Right click on one of the macro tags. Select Template Editor from the menu with a left click. The Template Editor window appears. You can create a symbol for your circuit. There may already be a default black box and if there is you can use it if you like, or you can delete it and draw one that you like.

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Chapter 1 — Computer Abstractions and Technology — 39 Creating a symbol for the new circuit

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Chapter 1 — Computer Abstractions and Technology — 40 Procedure for building the macro Once you have drawn an object or decided to use the default one you select the Pin Icon by left clicking. You then place the cursor where you want it to be in the diagram and left click to insert it. Next select it and right click and select associate with tag from the menu. Next close the template editor. You will notice a 1 next to the selected macro tag. Now select another macro tag, right click and select template editor and repeat the above procedure except for drawing the template. Do this for the remaining macro tags and then save the file. You do not use a separate name for the macro.

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Chapter 1 — Computer Abstractions and Technology — 41 Creating an interface point in the black box

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Chapter 1 — Computer Abstractions and Technology — 42 The completed black box representation

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Chapter 1 — Computer Abstractions and Technology — 43 The original circuit with the macro tags numbered

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Chapter 1 — Computer Abstractions and Technology — 44 Using a Macro Embedding a macro in a circuit

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Chapter 1 — Computer Abstractions and Technology — 45 Using a Macro continued You can use the push button interactive tool to insert inputs to the macro and the LED tool to insert outputs to the macro. You then wire the interactive buttons and LEDs to the appropriate macro icons. You can then run and test it. Suppose you want to build a circuit having more than one macro (which may or may not be the same) Select the embed macro button and position the cursor to where you want it in the workspace and left click.

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Chapter 1 — Computer Abstractions and Technology — 46 Embedding two macros, wiring them together

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Chapter 1 — Computer Abstractions and Technology — 47 Editing a macro in a circuit

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Chapter 1 — Computer Abstractions and Technology — 48 Editing the expanded form of the macro

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Chapter 1 — Computer Abstractions and Technology — 49

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Chapter 1 — Computer Abstractions and Technology — 50

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Chapter 1 — Computer Abstractions and Technology — 51 Decimal Codes Decimal 8421 Excess-3 digit code code 0 00000011 1 00010100 2 00100101 3 00110110 4 01000111 5 01011000 6 01101001 7 01111010 8 10001011 9 10011100

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Chapter 1 — Computer Abstractions and Technology — 52 Building a BCD adder Adding two single decimal digits given in 8421 BCD code can be accomplished by adding the 8421 representations as binary numbers. If there is no carry then the sum digit is exactly the binary sum and represents the 8421 representation of the two decimal digits. If there is a carry then this carry bit corresponds to 16 decimal and thus the correct two digit decimal number can be determined by subtracting 6 from the 5 th bit making it a 10 and adding the 6 into the first digit which is represented by the rightmost 4 digits. For example a sum of 18, given as 1 0010 = 16 + 2. If we count the leading 1 as the tens digit then we must add 6 + 2 to get 10 + 8 = 18, i.e. 16 – 6 = 10 and 0010 + 0110 = 1000. Now the 1 0010 = 0001 1000 as a 8421 BCD 2 digit number.

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Chapter 1 — Computer Abstractions and Technology — 53 Organization of a single-decade 8421 BCDdecimal adder.

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Chapter 1 — Computer Abstractions and Technology — 54 Organization of a single-decade 8421 BCD adder.

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Chapter 1 — Computer Abstractions and Technology — 55 Karnaugh map to detect the combinations P3P2P1P0 = 1010, 1011,..., 1111. P 3 P 2 + P 3 P 1 true implies one of the above combinations

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Chapter 1 — Computer Abstractions and Technology — 56 A single-decade 8421 BCD adder.

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Chapter 1 — Computer Abstractions and Technology — 57 Reading for next time PH 3: Chapter 5, sections 5.1-5.4

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