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Lecture 23: Registers and Counters (2)

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1 Lecture 23: Registers and Counters (2)
CPE 201 Digital Design Lecture 23: Registers and Counters (2)

2 Lecture Outline Counters

3 Counters Counter: a register that goes through a prescribed sequence of states Ripple counters: the flip-flop output triggers other flip-flops Synchronous counters count the clock

4 Counters N-bit up-counter: N-bit register that can increment (add 1) to its own value on each clock cycle 0000, 0001, 0010, 0011, ...., 1110, 1111, 0000 Note how count “rolls over” from 1111 to 0000 Terminal (last) count, tc, equals 1 during value just before rollover 1 c n t C 4-bit up-counter 4 0100 0101 0011 0000 0001 0010 0000 1111 1 0001 1110 ...

5 Binary Ripple Counter Binary Count Sequence A3 A2 A1 A0 0 0 0 0
A0 is complemented with each count pulse A1 is complemented when A0 goes from 1 to 0 A2 is complemented when A1 goes from 1 to 0 A3 is complemented when A2 goes from 1 to 0

6 Binary Ripple Counter Use complementing flip-flops, with negative-edge transition Connect the output of each flip-flop to the clock input of the next higher order flip-flop Examples of complementing flip-flops T flip-flop D flip-flop: with the output complement connected to the input JK flip-flop with both inputs connected to 1

7 Examples of Binary Ripple Counters

8 Binary Ripple Counter Count-down counter: A binary counter with reverse count: starts from 15 and goes down The least significant bit is complemented with every count pulse Any other bit is complemented if the previous bit goes from 0 to 1 We can use the same counter design (but with rising edge flip-flops) to make a count-down counter

9 4-bit Synchronous Binary Counters
A flip-flop is complemented if all lower bits are 1. A3 A2 A1 A0 ….

10 Binary Counter with Parallel Load
Count = 1, Load =0  This will provide appropriate JK inputs for all flip-flops, which enables counting 1 1 1 1 1 1 1 1 1 1

11 Binary Counter with Parallel Load
Count = 0, Load =1  This will provide the external inputs at the JK inputs for all flip-flops, which enables loading 1 1 I0 I0 1 I0’ I0’ 1 I1 I1 1 I1’ I1’ 1 I2 I2 1 I2’ I2’ 1 I3 I3 1 I3’ I3’

12 4-bit Up-Down Binary Counters
In a down binary counter The least significant bit is always complemented A bit is complemented if all lower bits are 0 Change an up counter to a down counter: The AND gates should come from the complement outputs instead of the normal ones Up = 1, Down =0: Circuit counts up since input comes from Normal output Up = 0, Down =1: Circuit counts down since input comes from Complemented output

13 Counter Example: Mode in Above-Mirror Display
Recall above-mirror display example Assumed component that incremented xy input each time button pressed: 00, 01, 10, 11, 00, 01, 10, 11, 00, ... Can use 2-bit up-counter Assumes mode=1 for just one clock cycle during each button press Recall “Button press synchronizer” example c n t c1 c0 x y 2-bit up ou er mode clk

14 Counter Example: 1 Hz Pulse Generator Using 256 Hz Oscillator
Suppose we have 256 Hz oscillator, but we want 1 Hz pulse 1 Hz is 1 pulse per second – useful for keeping time Design using 8-bit up-counter, use tc output as pulse Counts from 0 to 255 (256 counts), so pulses tc every 256 cycles c n t C (unused) 8-bit up-counter 1 osc (256 Hz) 8 p (1 Hz)

15 Counter Example: Light Sequencer
Illuminate 8 lights from right to left, one at a time, one per second Use 3-bit up-counter to count from 0 to 7 Use 3x8 decoder to illuminate appropriate light Note: Used 3-bit counter with 3x8 decoder NOT an 8-bit counter 3-bit u p - c ou n t er c2 c1 c0 3 x 8 d d i2 i1 i0 unused 1 clk (1 H z) d7 d6 d5 d4 d3 d2 d1 d0 1 1 lig h ts

16 Counters Alternative internal design
Register, incrementer, and N-input AND gate to detect terminal count ld 4-bit register C t c 4 n 4-bit up-counter +1

17 Incrementer Could use carry-ripple adder with B input set to 00...001
But when adding to another number, the leading 0’s obviously don’t need to be considered - so just two bits being added per column Use half-adders (add two bits) rather than full-adders (add three bits) ( a ) b a3 a2 a1 a0 1 s0 s1 s2 s3 c o s HA +1 0 1 1 1 + carries: unused

18 Down-Counter 4-bit down-counter Need decrementer (-1)
1111, 1110, 1101, 1100, …, 0011, 0010, 0001, 0000, 1111, … Need decrementer (-1) design similar to incrementer Terminal count is 0000 Use NOR gate to detect ld 4-bit register C 4 c n t 4-bit down-counter –1 t c

19 Up/Down-Counter Can count either up or down
Includes both incrementer and decrementer Use dir input to select, using 2x1: dir=0 means up Likewise, dir selects appropriate terminal count value ld 4-bit register C t c 4 n clr dir 4-bit up/down counter –1 +1 1 2 x 4-bit 2

20 Counter with Parallel Load
Up-counter that can be loaded with external value ld 4-bit register C t c 4 n +1 1 4-bit 2 x L Designed using 2x1 mux – ld input selects incremented value or external value Load the internal register when loading external value or when counting

21 Example with Down Counter
1000 Useful to create pulses at specific multiples of clock Not just at N-bit counter’s natural wrap-around of 2N E.g.: Pulse every 9 clock cycles Use 4-bit down-counter with parallel load Set parallel load input to 8 (1000) Use terminal count to reload When count reaches 0, next cycle loads 8 Why load 8 and not 9? Because 0 is included in count sequence: 8, 7, 6, 5, 4, 3, 2, 1, 0  9 counts c n t ld C L 1 clk 4 4-bit down-counter

22 Counter Example: New Year’s Eve Countdown Display
Count from 59 down to 0 in binary using microprocessor Can use 8-bit (or 7- or 6-bit) down-counter instead, initially loaded with 59 d0 i0 i1 i2 i3 i4 i5 d1 d2 d3 d58 d59 d60 d61 d62 d63 6x64 dcd Happy New Year 1 2 3 58 59 c0 c1 c2 c3 c4 c5 c6 c7 t c 8-bit down- counter 59 8 L ld n clk (1 Hz) reset fireworks countdown

23 Counter Example: 1 Hz Pulse Generator from 60 Hz Clock
Have 60 Hz signal Need device to convert that to 1 Hz signal to count seconds Use clear input Use 6-bit up-counter Can count from 0 to 63 Create simple logic to detect 59 (for 60 counts) Use to clear the counter back to 0 (or to load 0) C t c p 1 osc (60 Hz) (1 Hz) clr n 6-bit up counter

24 Readings Chapter 6 Sections 6.3 – 6.5

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