1. Charles Kime & Thomas Kaminski © 2008 Pearson Education, Inc. (Hyperlinks are active in View Show mode) Chapter 5 – Sequential Circuits Part 2 – Sequential Circuit Design Logic and Computer Design Fundamentals

2. Chapter 5 - Part 2 2 Overview  Part 1 - Storage Elements and Sequential Circuit Analysis  Part 2- Sequential Circuit Design  Specification  Formulation  State Assignment  Flip-Flop Input and Output Equation Determination  Verification  Part 3 – State Machine Design

3. Chapter 5 - Part 2 3 The Design Procedure  Specification  Formulation - Obtain a state diagram or state table  State Assignment - Assign binary codes to the states  Flip-Flop Input Equation Determination - Select flip-flop types and derive flip-flop equations from next state entries in the table  Output Equation Determination - Derive output equations from output entries in the table  Optimization - Optimize the equations  Technology Mapping - Find circuit from equations and map to flip-flops and gate technology  Verification - Verify correctness of final design

4. Chapter 5 - Part 2 4 Specification  Component Forms of Specification Written description Mathematical description Hardware description language* Tabular description* Equation description* Diagram describing operation (not just structure)*  Relation to Formulation If a specification is rigorous at the binary level (marked with * above), then all or part of formulation may be completed

5. Chapter 5 - Part 2 5 Formulation: Finding a State Diagram  A state is an abstraction of the history of the past applied inputs to the circuit (including power-up reset or system reset). The interpretation of “past inputs” is tied to the synchronous operation of the circuit. E. g., an input value (other than an asynchronous reset) is measured only during the setup-hold time interval for an edge-triggered flip-flop.  Examples: State A represents the fact that a 1 input has occurred among the past inputs. State B represents the fact that a 0 followed by a 1 have occurred as the most recent past two inputs.

6. Chapter 5 - Part 2 6 Formulation: Finding a State Diagram  In specifying a circuit, we use states to remember meaningful properties of past input sequences that are essential to predicting future output values.  A sequence recognizer is a sequential circuit that produces a distinct output value whenever a prescribed pattern of input symbols occur in sequence, i.e, recognizes an input sequence occurence.  We will develop a procedure specific to sequence recognizers to convert a problem statement into a state diagram.  Next, the state diagram, will be converted to a state table from which the circuit will be designed.

7. Counter Design Example  Circuit that counts in binary from 0 to 4 and repeats. Chapter 5 - Part 2 7 Combina- tional Logic Storage Elements Inputs Outputs State Next State O0O1O2O0O1O2

8. State Diagram Chapter 5 - Part 2 8 A O 0 = 0 O 1 = 0 O 2 = 0 B O 0 = 1 O 1 = 0 O 2 = 0 C O 0 = 0 O 1 = 1 O 2 = 0 D O 0 = 1 O 1 = 1 O 2 = 0 E O 0 = 0 O 1 = 0 O 2 = 1

9. Sate Table Chapter 5 - Part 2 9 Current State InputsNext StateOutputs O2O2 O1O1 O0O0 A B000 B C001 C D010 D E011 E A100

10. Sate code assignment Chapter 5 - Part 2 10 Current State Inputs Next State Outputs O2O2 O1O1 O0O0 A B000 B C001 C D010 D E011 E A100

11. Chapter 5 - Part 2 11 State Assignment  Each of the m states must be assigned a unique code  Minimum number of bits required is n such that n ≥ log 2 m where x is the smallest integer ≥ x  There are useful state assignments that use more than the minimum number of bits  There are 2 n - m unused states

12. Chapter 5 - Part 2 12  How may assignments of codes with a minimum number of bits? Two with A = 0, B = 1 or A = 1, B = 0  Does it make a difference? Only in variable inversion, so small, if any. State Assignment – Example

13. Chapter 5 - Part 2 13  How may assignments of codes with a minimum number of bits? Log(5) =3 with many possible assignments  Does it make a difference? Only in variable inversion, so small, if any. State Assignment – our example Current State InputsNext StateOutputs O2O2 O1O1 O0O0 A B000 B C001 C D010 D E011 E A100

14. Sate code assignment  Let A = 000; B = 001; C = 010; D = 011; E = 100 ( many other assignments are possible ). Chapter 5 - Part 2 14 Current StateInputsNext StateOutputs Q2Q2 Q1Q1 Q0Q0 D2D2 D1D1 D0D0 O2O2 O1O1 O0O0 A=000 B=001000 001 C=010001 010 D=011010 011 E=100011 100 A=000100

15. Unused state codes  A state table MUST list all combinations Chapter 5 - Part 2 15 Current StateInputsNext StateOutputs Q2Q2 Q1Q1 Q0Q0 D2D2 D1D1 D0D0 O2O2 O1O1 O0O0 A000 B001000 B001 C010001 C010 D011010 D011 E100011 E100 A000100 101 X X X XX X 110 X X X XX X 111 X X X XX X Unused Use Don’t cares

16. Find Boolean equations  O 0 = Q 2 Q 1 Q 0 + Q 2 Q 1 Q 0  O 1 = Q 2 Q 1 Q 0 + Q 2 Q 1 Q 0  O 2 = Q 2 Q 1 Q 0 Chapter 5 - Part 2 16 Current StateInputsNext StateOutputs Q2Q2 Q1Q1 Q0Q0 D2D2 D1D1 D0D0 O2O2 O1O1 O0O0 A=000 B=001000 001 C=010001 010 D=011010 011 E=100011 100 A=000100  D 0 = Q 2 Q 1 Q 0 + Q 2 Q 1 Q 0  D 1 = Q 2 Q 1 Q 0 + Q 2 Q 1 Q 0  D 2 = Q 2 Q 1 Q 0 Next State Functions Output Functions

17. Simplify with Karnaugh map (outputs) Chapter 5 - Part 2 17 Q1Q0 Q2,00,011110 00000 11XXX Q1Q0 Q2,00,011110 00011 10XXX Q1Q0 Q2,00,011110 00110 10XXX Current State InNext StateOutputs Q2Q2 Q1Q1 Q0Q0 D2D2 D1D1 D0D0 O2O2 O1O1 O0O0 A000 B001000 B001 C010001 C010 D011010 D011 E100011 E100 A000100 101 X X X XX X 110 X X X XX X 111 X X X XX X O2O2 O1O1 O0O0

18. Simplified output functions Chapter 5 - Part 2 18 Q1Q0 Q2,00,011110 00000 11XXX Q1Q0 Q2,00,011110 00011 10XXX Q1Q0 Q2,00,011110 00110 10XXX O2O2 O1O1 O0O0  New:  O 0 = Q 0  O 1 = Q 1  O 2 = Q 2  Old  O 0 = Q 2 Q 1 Q 0 + Q 2 Q 1 Q 0  O 1 = Q 2 Q 1 Q 0 + Q 2 Q 1 Q 0  O 2 = Q 2 Q 1 Q 0

19. Simplify Next State Functions Chapter 5 - Part 2 19 Q1Q0 Q2,00,011110 00010 10XXX Q1Q0 Q2,00,011110 00101 10XXX Q1Q0 Q2,00,011110 01001 10XXX Current State InNext StateOutputs Q2Q2 Q1Q1 Q0Q0 D2D2 D1D1 D0D0 O2O2 O1O1 O0O0 A000 B001000 B001 C010001 C010 D011010 D011 E100011 E100 A000100 101 X X X XX X 110 X X X XX X 111 X X X XX X D2D2 D1D1 D0D0

20. Simplified Next State Functions Chapter 5 - Part 2 20 Q1Q0 Q2,00,011110 00010 10XXX Q1Q0 Q2,00,011110 00101 10XXX Q1Q0 Q2,00,011110 01001 10XXX D2D2 D1D1 D0D0  D 0 = Q 2 Q 1 Q 0 + Q 2 Q 1 Q 0  D 1 = Q 2 Q 1 Q 0 + Q 2 Q 1 Q 0  D 2 = Q 2 Q 1 Q 0  Old  New:  D 0 = Q 2 Q 0  D 1 = Q 1 Q 0 + Q 1 Q 0  D 2 = Q 1 Q 0

21. Implement sequential circuit Chapter 5 - Part 2 21 Clock Reset D Q C Q R D Q C Q R D Q C Q R 2 1 0 Q0Q0 Q1Q1 Q2Q2 Q1Q1 Q0Q0 O2O2 O1O1 O0O0 Q0Q0 Q2Q2  D 0 = Q 2 Q 0  D 1 = Q 1 Q 0 + Q 1 Q 0  D 2 = Q 1 Q 0

22. Chapter 5 - Part 2 22 Sequence Recognizer Procedure  To develop a sequence recognizer state diagram: Begin in an initial state in which NONE of the initial portion of the sequence has occurred (typically “reset” state). Add a state that recognizes that the first symbol has occurred. Add states that recognize each successive symbol occurring. The final state represents the input sequence (possibly less the final input value) occurence. Add state transition arcs which specify what happens when a symbol not in the proper sequence has occurred. Add other arcs on non-sequence inputs which transition to states that represent the input subsequence that has occurred.  The last step is required because the circuit must recognize the input sequence regardless of where it occurs within the overall sequence applied since “reset.”.

23. Chapter 5 - Part 2 23 Sequence Recognizer Example  Example: Recognize the sequence 1101 Note that the sequence 1111101 contains 1101 and "11" is a proper sub-sequence of the sequence.  Thus, the sequential machine must remember that the first two one's have occurred as it receives another symbol.  Also, the sequence 1101101 contains 1101 as both an initial subsequence and a final subsequence with some overlap, i. e., 1101101 or 1101101.  And, the 1 in the middle, 1101101, is in both subsequences.  The sequence 1101 must be recognized each time it occurs in the input sequence.

24. Chapter 5 - Part 2 24 Example: Recognize 1101  Define states for the sequence to be recognized: assuming it starts with first symbol, continues through each symbol in the sequence to be recognized, and uses output 1 to mean the full sequence has occurred, with output 0 otherwise.  Starting in the initial state (Arbitrarily named "A"): Add a state that recognizes the first "1." State "A" is the initial state, and state "B" is the state which represents the fact that the "first" one in the input subsequence has occurred. The output symbol "0" means that the full recognized sequence has not yet occurred. A B 1/0

25. Chapter 5 - Part 2 25  After one more 1, we have: C is the state obtained when the input sequence has two "1"s.  Finally, after 110 and a 1, we have: Transition arcs are used to denote the output function (Mealy Model) Output 1 on the arc from D means the sequence has been recognized To what state should the arc from state D go? Remember: 1101101 ? Note that D is the last state but the output 1 occurs for the input applied in D. This is the case when a Mealy model is assumed. Example: Recognize 1101 (continued) A B 1/0 A B C 0/0 C 1/0 D 1/1

26. Chapter 5 - Part 2 26 Example: Recognize 1101 (continued)  Clearly the final 1 in the recognized sequence 1101 is a sub-sequence of 1101. It follows a 0 which is not a sub-sequence of 1101. Thus it should represent the same state reached from the initial state after a first 1 is observed. We obtain: A B 1/0 C 0/0 1/1 D AB 1/0 C 0/0 D 1/1

27. Chapter 5 - Part 2 27 Example: Recognize 1101 (continued)  The state have the following abstract meanings: A: No proper sub-sequence of the sequence has occurred. B: The sub-sequence 1 has occurred. C: The sub-sequence 11 has occurred. D: The sub-sequence 110 has occurred. The 1/1 on the arc from D to B means that the last 1 has occurred and thus, the sequence is recognized. 1/1 AB 1/0 C D 0/0

28. Chapter 5 - Part 2 28 Example: Recognize 1101 (continued)  The other arcs are added to each state for inputs not yet listed. Which arcs are missing?  Answer: "0" arc from A "0" arc from B "1" arc from C "0" arc from D. 1/1 AB 1/0 C D 0/0

29. Chapter 5 - Part 2 29 Example: Recognize 1101 (continued)  State transition arcs must represent the fact that an input subsequence has occurred. Thus we get:  Note that the 1 arc from state C to state C implies that State C means two or more 1's have occurred. C 1/1 A B 1/0 D 0/0 1/0 0/0

30. Chapter 5 - Part 2 30 Formulation: Find State Table  From the State Diagram, we can fill in the State Table.  There are 4 states, one input, and one output. We will choose the form with four rows, one for each current state.  From State A, the 0 and 1 input transitions have been filled in along with the outputs. 1/0 0/0 1/1 AB 1/0 C D 0/0 1/0 B 0 0/0 A 0

31. Chapter 5 - Part 2 31 State Present Formulation: Find State Table  From the state diagram, we complete the state table.  What would the state diagram and state table look like for the Moore model? 1/00/0 1/1 AB 1/0 C D 0/0 Next State x=0 x=1 Output x=0 x=1 A A B 0 B A C0 C D C 0 D A B 0 1

32. Chapter 5 - Part 2 32 Example: Moore Model for Sequence 1101  For the Moore Model, outputs are associated with states.  We need to add a state "E" with output value 1 for the final 1 in the recognized input sequence. This new state E, though similar to B, would generate an output of 1 and thus be different from B.  The Moore model for a sequence recognizer usually has more states than the Mealy model.

33. Chapter 5 - Part 2 33 Example: Moore Model (continued)  We mark outputs on states for Moore model  Arcs now show only state transitions  Add a new state E to produce the output 1  Note that the new state, E produces the same behavior in the future as state B. But it gives a different output at the present time. Thus these states do represent a different abstraction of the input history. A/0B/0 C/0D/0 0 E/1 0 0 0 11 1 1 10

34. Chapter 5 - Part 2 34 Example: Moore Model (continued)  The state table is shown below  Memory aid re more state in the Moore model: “Moore is More.” A/0B/0 C/0D/0 0 E/1 0 0 0 11 1 1 10

35. Chapter 5 - Part 2 35  How may assignments of codes with a minimum number of bits? 4  3  2  1 = 24  Does code assignment make a difference in cost? State Assignment – Example 2

36. Chapter 5 - Part 2 36  Counting Order Assignment: A = 0 0, B = 0 1, C = 1 0, D = 1 1  The resulting coded state table: State Assignment – Example 2 (continued) Present State Next State x = 0 x = 1 Output x = 0 x = 1 0 0 100 0 1 000 1 1 000 1 0 0 101

37. Chapter 5 - Part 2 37  Gray Code Assignment: A = 0 0, B = 0 1, C = 1 1, D = 1 0  The resulting coded state table: State Assignment – Example 2 (continued) Present State Next State x = 0 x = 1 Output x = 0 x = 1 0 0 100 0 1 00 1 01 00 1 00 0 101

38. Chapter 5 - Part 2 38 Find Flip-Flop Input and Output Equations: Example 2 – Counting Order Assignment Y2Y2 Y1Y1 X 1 0 0 0 00 0 0 Y2Y2 Y1Y1 X 0 0 1 0 10 0 1 Y2Y2 Y1Y1 X 1 0 0 0 00 1 1 D1D1 D2D2 Z  Assume D flip-flops  Interchange the bottom two rows of the state table, to obtain K-maps for D 1, D 2, and Z:

39. Chapter 5 - Part 2 39 Optimization: Example 2: Counting Order Assignment  Performing two-level optimization: D 1 = Y 1 Y 2 + XY 1 Y 2 D 2 = XY 1 Y 2 + XY 1 Y 2 + XY 1 Y 2 Z = XY 1 Y 2 Gate Input Cost = 22 Y2Y2 Y1Y1 X 1 0 0 0 00 0 0 Y2Y2 Y1Y1 X 0 0 1 0 10 0 1 Y2Y2 Y1Y1 X 1 0 0 0 00 1 1 D1D1 D2D2 Z

40. Chapter 5 - Part 2 40 Find Flip-Flop Input and Output Equations: Example 2 – Gray Code Assignment Y2Y2 Y1Y1 X 1 0 0 0 00 0 0 Y2Y2 Y1Y1 X 1 0 1 0 10 1 0 Y2Y2 Y1Y1 X 0 0 0 0 11 1 0  Assume D flip-flops  Obtain K-maps for D 1, D 2, and Z: D1D1 D2D2 Z

41. Chapter 5 - Part 2 41 Optimization: Example 2: Assignment 2  Performing two-level optimization: D 1 = Y 1 Y 2 + XY 2 Gate Input Cost = 9 D 2 = X Select this state assignment to Z = XY 1 Y 2 complete design in slide Y2Y2 Y1Y1 X 1 0 0 0 00 0 0 Y2Y2 Y1Y1 X 1 0 1 0 10 1 0 Y2Y2 Y1Y1 X 0 0 0 0 11 1 0 D1D1 D2D2 Z

42. Chapter 5 - Part 2 42 One Flip-flop per State (One-Hot) Assignment  Example codes for four states: (Y 3, Y 2, Y 1, Y 0 ) = 0001, 0010, 0100, and 1000.  In equations, need to include only the variable that is 1 for the state, e. g., state with code 0001, is represented in equations by Y 0 instead of Y 3 Y 2 Y 1 Y 0 because all codes with 0 or two or more 1s have don’t care next state values.  Provides simplified analysis and design  Combinational logic may be simpler, but flip- flop cost higher – may or may not be lower cost

43. Chapter 5 - Part 2 43  One-Hot Assignment : A = 0001, B = 0010, C = 0100, D = 1000 The resulting coded state table: State Assignment – Example 2 (continued) Present State Next State x = 0 x = 1 Output x = 0 x = 1 0001 001000 0001010000 1000010000 10000001001001

44. Chapter 5 - Part 2 44 Optimization: Example 2: One Hot Assignment  Equations read from 1 next state variable entries in table: D 0 = X(Y 0 + Y 1 + Y 3 ) or X Y 2 D 1 = X(Y 0 + Y 3 ) D 2 = X(Y 1 + Y 2 ) or X(Y 0 + Y 3 ) D 3 = X Y 2 Z = XY 3 Gate Input Cost = 15  Combinational cost intermediate plus cost of two more flip-flops needed.

45. Chapter 5 - Part 2 45  Library: D Flip-flops with Reset (not inverted) NAND gates with up to 4 inputs and inverters  Initial Circuit: Map Technology Clock D D C R Y2Y2 Z C R Y1Y1 X Reset

46. Chapter 5 - Part 2 46 Mapped Circuit - Final Result Clock D D C R Y2Y2 Z C R Y1Y1 X Reset

47. Chapter 5 - Part 2 47 Sequential Design: Example 3  Design a sequential modulo 3 accumulator for 2- bit operands  Definitions: Modulo n adder - an adder that gives the result of the addition as the remainder of the sum divided by n  Example: 2 + 2 modulo 3 = remainder of 4/3 = 1 Accumulator - a circuit that “accumulates” the sum of its input operands over time - it adds each input operand to the stored sum, which is initially 0.  Stored sum: (Y 1,Y 0 ), Input: (X 1,X 0 ), Output: (Z 1,Z 0 )

48. Chapter 5 - Part 2 48 Example 3 (continued)  Complete the state diagram: B/01 C/10 A/00 00 01 Reset

49. Chapter 5 - Part 2 49 Example 3 (continued)  Complete the state table  State Assignment: (Y 1,Y 0 ) = (Z 1,Z 0 )  Codes are in gray code order to ease use of K-maps in the next step 00011110Z1Z0Z1Z0 Y 1 (t+1), Y 0 (t+1) A (00)00X B (01)X01 - (11)XXXX11 C (10)X10 X1X0X1X0 Y1Y0Y1Y0

50. Chapter 5 - Part 2 50 Example 3 (continued)  Find optimized flip-flop input equations for D flip-flops  D 1 =  D 0 = D0D0 D1D1 Y0Y0 Y1Y1 X1X1 X0X0 Y0Y0 Y1Y1 X1X1 X X0X0 X X X X X X X X X X X X X

51. Chapter 5 - Part 2 51 Circuit - Final Result with AND, OR, NOT Clock D C R Y0Y0 D C R Y1Y1 X1X1 Reset Z1Z1 X0X0 Z0Z0

52. Chapter 5 - Part 2 52 Other Flip-Flop Types  J-K and T flip-flops Behavior Implementation  Basic descriptors for understanding and using different flip-flop types Characteristic tables Characteristic equations Excitation tables  For actual use, see Reading Supplement - Design and Analysis Using J-K and T Flip-Flops

53. Chapter 5 - Part 2 53 J-K Flip-flop  Behavior Same as S-R flip-flop with J analogous to S and K analogous to R Except that J = K = 1 is allowed, and For J = K = 1, the flip-flop changes to the opposite state As a master-slave, has same “1s catching” behavior as S-R flip-flop If the master changes to the wrong state, that state will be passed to the slave  E.g., if master falsely set by J = 1, K = 1 cannot reset it during the current clock cycle

54. Chapter 5 - Part 2 54 J-K Flip-flop (continued)  Implementation To avoid 1s catching behavior, one solution used is to use an edge-triggered D as the core of the flip-flop  Symbol D C K J J C K

55. Chapter 5 - Part 2 55 T Flip-flop  Behavior Has a single input T  For T = 0, no change to state  For T = 1, changes to opposite state  Same as a J-K flip-flop with J = K = T  As a master-slave, has same “1s catching” behavior as J-K flip-flop  Cannot be initialized to a known state using the T input Reset (asynchronous or synchronous) essential

56. Chapter 5 - Part 2 56 T Flip-flop (continued)  Implementation To avoid 1s catching behavior, one solution used is to use an edge-triggered D as the core of the flip-flop  Symbol C D T T C

57. Chapter 5 - Part 2 57 Basic Flip-Flop Descriptors  Used in analysis Characteristic table - defines the next state of the flip-flop in terms of flip-flop inputs and current state Characteristic equation - defines the next state of the flip-flop as a Boolean function of the flip-flop inputs and the current state  Used in design Excitation table - defines the flip-flop input variable values as function of the current state and next state

58. Chapter 5 - Part 2 58 D Flip-Flop Descriptors  Characteristic Table  Characteristic Equation Q(t+1) = D  Excitation Table D 0 1 Operation Reset Set 0 1 Q(t1) + Q(t+1) 0 1 0 1 D Operation Reset Set

59. Chapter 5 - Part 2 59 T Flip-Flop Descriptors  Characteristic Table  Characteristic Equation Q(t+1) = T  Q  Excitation Table No change Complement Operation 0 1 TQ(t1) Q(t) Q(t) + Q(t + 1) Q(t) 1 0 T No change Complement Operation Q(t)

60. Chapter 5 - Part 2 60 S-R Flip-Flop Descriptors  Characteristic Table  Characteristic Equation Q(t+1) = S + R Q, S. R = 0  Excitation Table 0 0 1 1 OperationS 0 1 0 1 R No change Reset Set Undefined 0 1 ? Q(t+1) Q(t) Operation No change Set Reset No change S X 0 1 0 Q(t+ 1) 0 1 1 0 Q(t) 0 0 1 1 R X 0 1 0

61. Chapter 5 - Part 2 61 J-K Flip-Flop Descriptors  Characteristic Table  Characteristic Equation Q(t+1) = J Q + K Q  Excitation Table 0 0 1 1 No change Set Reset Complement OperationJ 0 1 0 1 K 0 1 Q(t +1) Q(t) Q(t) Q(t + 1) 0 1 1 0 Q(t) 0 0 1 1 Operation X X 0 1 K 0 1 X X J No change Set Reset No Change

62. Chapter 5 - Part 2 62 Flip-flop Behavior Example  Use the characteristic tables to find the output waveforms for the flip-flops shown: T C Clock D,T QDQD QTQT D C

63. Chapter 5 - Part 2 63 Flip-Flop Behavior Example (continued)  Use the characteristic tables to find the output waveforms for the flip-flops shown: J C K S C R Clock S,J Q SR Q JK R,K ?

64. Chapter 5 - Part 2 64 Terms of Use  All (or portions) of this material © 2008 by Pearson Education, Inc.  Permission is given to incorporate this material or adaptations thereof into classroom presentations and handouts to instructors in courses adopting the latest edition of Logic and Computer Design Fundamentals as the course textbook.  These materials or adaptations thereof are not to be sold or otherwise offered for consideration.  This Terms of Use slide or page is to be included within the original materials or any adaptations thereof.