1. Caltech CS184 Winter2005 -- DeHon 1 CS184a: Computer Architecture (Structure and Organization) Day 6: January 19, 2005 VLSI Scaling

2. Caltech CS184 Winter2005 -- DeHon 2 Today VLSI Scaling Rules Effects Historical/predicted scaling Variations (cheating) Limits

3. Caltech CS184 Winter2005 -- DeHon 3 Why Care? In this game, we must be able to predict the future Rapid technology advance Reason about changes and trends re-evaluate prior solutions given technology at time X.

4. Caltech CS184 Winter2005 -- DeHon 4 Why Care Cannot compare against what competitor does today –but what they can do at time you can ship Careful not to fall off curve –lose out to someone who can stay on curve

5. Caltech CS184 Winter2005 -- DeHon 5 Scaling Premise: features scale “uniformly” –everything gets better in a predictable manner Parameters:   (lambda) -- Mead and Conway (class)  S -- Bohr  1/  -- Dennard

6. Caltech CS184 Winter2005 -- DeHon 6 Feature Size is half the minimum feature size in a VLSI process [minimum feature usually channel width]

7. Caltech CS184 Winter2005 -- DeHon 7 Scaling Channel Length (L) Channel Width (W) Oxide Thickness (T ox ) Doping (N a ) Voltage (V)

8. Caltech CS184 Winter2005 -- DeHon 8 Scaling Channel Length (L) Channel Width (W) Oxide Thickness (T ox ) Doping (N a ) 1/ Voltage (V)

9. Caltech CS184 Winter2005 -- DeHon 9 Effects? Area Capacitance Resistance Threshold (V th ) Current (I d ) Gate Delay (  gd ) Wire Delay (  wire ) Power

10. Caltech CS184 Winter2005 -- DeHon 10 Area       L * W       130nm   90nm  50% area  2x capacity same area

11. Caltech CS184 Winter2005 -- DeHon 11 Area Perspective

12. Caltech CS184 Winter2005 -- DeHon 12 Capacity Scaling from Intel

13. Caltech CS184 Winter2005 -- DeHon 13 Capacitance Capacitance per unit area –C ox =  SiO 2 /T ox –T ox   T ox /  –C ox   C ox

14. Caltech CS184 Winter2005 -- DeHon 14 Capacitance Gate Capacitance  C gate = A*C ox       C ox   C ox  C gate   C gate / 

15. Caltech CS184 Winter2005 -- DeHon 15 Threshold Voltage

16. Caltech CS184 Winter2005 -- DeHon 16 Threshold Voltage V TH   V TH 

17. Caltech CS184 Winter2005 -- DeHon 17 Current Saturation Current I d =(  C OX /2)(W/L)(V gs -V TH ) 2 V gs= V   V  V TH   V TH  W   W  L   L  C ox   C ox I d   I d 

18. Caltech CS184 Winter2005 -- DeHon 18 Gate Delay   gd =Q/I=(CV)/I  V   V   I d   I d  C C /C C /   gd   gd / 

19. Caltech CS184 Winter2005 -- DeHon 19 Resistance R=  L/(W*t) W   W  L, t similar R   R

20. Caltech CS184 Winter2005 -- DeHon 20 Wire Delay   wire =R  C  R  R  C  C /    wire  wire …assuming (logical) wire lengths remain constant... Assume short wire or buffered wire (unbuffered wire ultimately scales as length squared)

21. Caltech CS184 Winter2005 -- DeHon 21 Power Dissipation (Static Load) Resistive Power –P=V*I –V   V  –I d   I d  –P   P  

22. Caltech CS184 Winter2005 -- DeHon 22 Power Dissipation (Dynamic) Capacitive (Dis)charging  P=(1/2)CV 2 f  V   V   C   C /   P   P   Increase Frequency?   gd   gd /   So: f   f ?  P   P  

23. Caltech CS184 Winter2005 -- DeHon 23 Effects? Area 1/   Capacitance 1/  Resistance  Threshold (V th ) 1/  Current (I d ) 1/  Gate Delay (  gd ) 1/  Wire Delay (  wire ) 1 Power 1/     1/  

24. Caltech CS184 Winter2005 -- DeHon 24 ITRS Roadmap Semiconductor Industry rides this scaling curve Try to predict where industry going –(requirements…self fulfilling prophecy) http://public.itrs.net

25. Caltech CS184 Winter2005 -- DeHon 25 MOS Transistor Scaling (1974 to present) S=0.7 [0.5x per 2 nodes] Pitch Gate Source: 2001 ITRS - Exec. Summary, ORTC Figure [from Andrew Kahng]

26. Caltech CS184 Winter2005 -- DeHon 26 Half Pitch (= Pitch/2) Definition (Typical MPU/ASIC) (Typical DRAM) Poly Pitch Metal Pitch Source: 2001 ITRS - Exec. Summary, ORTC Figure [from Andrew Kahng]

27. Caltech CS184 Winter2005 -- DeHon 27 250 -> 180 -> 130 -> 90 -> 65 -> 45 -> 32 -> 22 -> 16 0.5x 0.7x NN+1N+2 Node Cycle Time (T yrs): *CARR(T) = [(0.5)^(1/2T yrs)] - 1 CARR(3 yrs) = -10.9% CARR(2 yrs) = -15.9% * CARR(T) = Compound Annual Reduction Rate (@ cycle time period, T) Log Half-Pitch Linear Time 1994 NTRS -.7x/3yrs Actual -.7x/2yrs Scaling Calculator + Node Cycle Time: Source: 2001 ITRS - Exec. Summary, ORTC Figure [from Andrew Kahng]

28. Caltech CS184 Winter2005 -- DeHon 28 Source: 2001 ITRS - Exec. Summary, ORTC Figure [from Andrew Kahng]

29. Caltech CS184 Winter2005 -- DeHon 29 ITRS 2003 Gate/Wire Scaling

30. Caltech CS184 Winter2005 -- DeHon 30 What happens to delays? If delays in gates/switching? If delays in interconnect? Logical interconnect lengths?

31. Caltech CS184 Winter2005 -- DeHon 31 Delays? If delays in gates/switching? –Delay reduce with 1/ 

32. Caltech CS184 Winter2005 -- DeHon 32 Delays Logical capacities growing Wirelengths? –No locallity: L   (slower!) –Rent’s Rule L   n (p-0.5) [p>0.5]

33. Caltech CS184 Winter2005 -- DeHon 33 Compute Density Density = compute / (Area * Time)   >compute density scaling>     gates dominate, p<0.5    moderate p, good fraction of gate delay –[p from Rent’s Rule again – more on Day12]    large p (wires dominate area and delay)

34. Caltech CS184 Winter2005 -- DeHon 34 Power Density P  P   (static, or increase frequency) P  P   (dynamic, same freq.) A  A   P/A   P/A … or … P/  A

35. Caltech CS184 Winter2005 -- DeHon 35 Cheating… Don’t like some of the implications –High resistance wires –Higher capacitance –Quantum tunnelling –Need for more wiring –Not scale speed fast enough

36. Caltech CS184 Winter2005 -- DeHon 36 Improving Resistance R=  L/(W*t) W   W  L, t similar R   R  Don’t scale t quite as fast.  Decrease  (copper)

37. Caltech CS184 Winter2005 -- DeHon 37 Capacitance and Leakage Capacitance per unit area –C ox =  SiO 2 /T ox –T ox   T ox /  –C ox   C ox Reduce Dielectric Constant  (interconnect) or Substitute for scaling T ox (gate quantum tunneling)

38. Caltech CS184 Winter2005 -- DeHon 38 Threshold Voltage

39. Caltech CS184 Winter2005 -- DeHon 39 ITRS 2003 Table 81a

40. Caltech CS184 Winter2005 -- DeHon 40 High-K dielectric Survey Wong/IBM J. of R&D, V46N2/3P133--168

41. Caltech CS184 Winter2005 -- DeHon 41 Wire Layers = More Wiring

42. Caltech CS184 Winter2005 -- DeHon 42 Wire Via Global (up to 5) Intermediate (up to 4) Local (2) Passivation Dielectric Etch Stop Layer Dielectric Capping Layer Copper Conductor with Barrier/Nucleation Layer Pre Metal Dielectric Tungsten Contact Plug Typical chip cross-section illustrating hierarchical scaling methodology [from Andrew Kahng]

43. Caltech CS184 Winter2005 -- DeHon 43 Improving Gate Delay   gd =Q/I=(CV)/I  V   V   I d =(  C OX /2)(W/L)(V gs -V TH ) 2  I d   I d  C C /C C /   gd   gd /   Lower C.  Don’t scale V. Don’t scale V: V  V I   I  gd   gd /  2

44. Caltech CS184 Winter2005 -- DeHon 44 …But Power Dissipation (Dynamic) Capacitive (Dis)charging  P=(1/2)CV 2 f  V   V   C   C /   P   P   Increase Frequency?  f   f ?  P   P   If not scale V, power dissipation not scale.

45. Caltech CS184 Winter2005 -- DeHon 45 …And Power Density P   P (increase frequency) P   P   (dynamic, same freq.)     P/A   P/A … or …   P/A Power Density Increases …this is where some companies have gotten into trouble…

46. Caltech CS184 Winter2005 -- DeHon 46 Physical Limits Doping? Features?

47. Caltech CS184 Winter2005 -- DeHon 47 Physical Limits Depended on –bulk effects doping current (many electrons) mean free path in conductor –localized to conductors Eventually –single electrons, atoms –distances close enough to allow tunneling

48. Caltech CS184 Winter2005 -- DeHon 48 What Is A “Red Brick” ? Red Brick = ITRS Technology Requirement with no known solution Alternate definition: Red Brick = something that REQUIRES billions of dollars in R&D investment [from Andrew Kahng]

49. Caltech CS184 Winter2005 -- DeHon 49 The “ Red Brick Wall ” - 2001 ITRS vs 1999 Source: Semiconductor International - http://www.e-insite.net/semiconductor/index.asp?layout=article&articleId=CA187876 [from Andrew Kahng]

50. Caltech CS184 Winter2005 -- DeHon 50 Conventional Scaling Ends in your lifetime …perhaps in your first few years after grad school…

51. Caltech CS184 Winter2005 -- DeHon 51 Finishing Up...

52. Caltech CS184 Winter2005 -- DeHon 52 Big Ideas [MSB Ideas] Moderately predictable VLSI Scaling –unprecedented capacities/capability growth for engineered systems –change –be prepared to exploit –account for in comparing across time –…but not for much longer

53. Caltech CS184 Winter2005 -- DeHon 53 Big Ideas [MSB-1 Ideas] Uniform scaling reasonably accurate for past couple of decades Area increase   –Real capacity maybe a little less? Gate delay decreases (1/  ) Wire delay not decrease, maybe increase Overall delay decrease less than (1/  )