1. . FUTURE of MICROELECTRONIC TECHNOLOGIES FROM SINGLE TRANSISTORS to INTEGRATED IMAGERS NEWS from INTERNATIONAL ELECTRON DEVICES MEETING Washington, 2-5 Dec 2001 Erik H.M. HEIJNE CERN EP Division BDI Forum 19 March 2002

2. . SILICON TECHNOLOGY for PARTICLE PHYSICS LOW NOISE ELECTRONICS HIGH FUNCTIONAL DENSITY SMART READOUT + SENSORS with PRECISE GEOMETRY HIGH SPEED (ns) APPLICATIONS for BEAM INSTRUMENTATION ?

3. . CONTENTS SCALING MOS TRANSISTORS PROSPECTS at IEDM 2001 TECHNOLOGY NODES SHORT TRANSISTORS CMOS DESIGN for LHC EXPERIMENTS ‘QUANTUM’ IMAGING RADIATION HARDNESS DEVELOPMENTS in IMAGERS NEWS IEDM 2001& ISSCC 2002 EXAMPLES CCD PHILIPS cs CCD LINCOLN LABS MIT (other) DISCUSSION

4. . HIGHLIGHTS - TRANSISTORS with L= 15-25 nm competition INTEL, IBM, AMD, ST session 29 - CONVICTION that <30 nm is SOI DIFFERENT APPROACHES --> DOUBLE GATE - MANY TECHNOLOGY CHANGES GATE MATERIAL W, Ti DIELECTRIC compounds, mixtures ? INTERCONNECTS Cu, optical CHANNEL Ultra-Thin, SON, SiGe - MEMORY trench : AR 60, ~7 µm - SYSTEM-on-a-CHIP : SOC - SENSORS 5 sessions - NEW ROADMAP : ITRS 2001 scaling accelerated

5. . BASIC DEVICES CONTACT METAL-SEMICONDUCTOR CONTACT (RECTIFYING, Schottky barrier) OHMIC CONTACT (non-injecting) CAPACITOR MIS / MOS METAL or POLY-Si OXIDE or low-k DIELECTRIC JUNCTION ALLOYED, DIFFUSED, ION-IMPLANTED TRANSISTOR 2 JUNCTIONS, BACK to BACK CCD is CAPACITOR ARRAY ALL TOGETHER ---> IC

6. . MOS TRANSISTOR CURRENT FIELDDRAIN SOURCE ACTIVE REGION GATE poly-SiLENGTH L WIDTH

7. . MOS TRANSISTOR ~ 1985 : LENGTH FEW µm, OXIDE GATE 100 nm -->50 nm LENGTH POLY GATE WIDTH DRAIN SOURCE CHANNEL (INVERSION LAYER) GATE OXIDE BULK Si

8. . CARRIER TRANSIT TIME Si :  e 600 cm 2 /Vs 1 µm 2V transit time ~ 13 ps SHORTER CHANNEL --> FASTER TRANSISTOR SEVERAL LIMITING FACTORS SMALLER DIMENSIONS NEED HIGHER DOPING --> THEN µ IS DEGRADED DRIFT VELOCITY SATURATES ETC. SWITCHING SPEED DEPENDS ALSO ON INTERNAL + EXTERNAL CAPACITANCES

9. . SPEED Si :  e 1500 --> 200 cm 2 /Vs CARRIER MOBILITY vs DOPING Si GaAs Ge

10. . TRANSISTOR SCALING INCREASE in SPEED RF now POSSIBLE on Si LOWER COST per FUNCTION MORE FUNCTIONS on SAME AREA SYSTEM on CHIP SoC

11. . sub - 70 nm SHORT COURSE DEVICE DESIGN Yuan TAUR now UCSD LITHOGRAPHY Luc Van den HOVE IMEC PROCESS INTEGRATION ISOLATION, JUNCTIONS and SILICIDES Liang-Kai HAN TSMC GATE DIELECTRICS and GATE MATERIALS Hsing-Huang TSENG Motorola MANUFACTURING and YIELD AT THE 70 nm NODE Chris J. McDONALD INTEL

12. . TECHNOLOGY NODES SHORTER TRANSISTORS can be INTRODUCED as add-on eg 70 nm in 130 nm NODE NODES DEFINED BY LITHOGRAPHY 'SECUNDARY' CHANGES DEPEND ON FOUNDRY eg Cu from 130 nm for IBM non-SiO 2 DIELECTRIC 300 mm wafer size

13. . sub - 70 nm SHORT COURSE Yuan TAUR CMOS SCALING

14. . Gates Deep-submicron CMOS New gate oxides ( < 2 nm ) have to be tested for radiation response MOS Gate TEM Bell Labs April 2000 Si SiO 2 1.6 nm Poly Si Reliable oxides can be made already with only ~ 6 atoms in SiO 2 layer SiO 2 CMOS technology used for 0.08 µm --> 0.02 µm? transistors ? NEW GATE METALS ? NEW DIELECTRICS ! mobility

15. . SHORT TRANSISTORS HOW TO PREVENT SHORT CHANNEL EFFECTS NEED VERY HIGH DOPING 10 19 cm - 3 GOOD OFF-CURRENT AT LOWER VDD BETTER SERIES R SUPER-HALO

16. . INTEL 50nm ‘DST’ DEPLETED SUBSTRATE TRANSISTOR 30 nm THIN Si SUBSTRATE on 200 nm OX RAISED SOURCE & DRAIN REDUCE R µ n MOBILITY ~ 300 HIGH Vt EQUIVALENT GATE OXIDE 1.5 nm NOTE REDUCTION µ At HIGH-FIELD 0.4 MV/cm --->2V/50nm

17. . IBM sub-40nm SOI SUB-40nm TRANSISTOR at 70nm NODE >1000 µA /µm for nFET OFF < 100 nA @ 1.1V Si SUBSTRATE nFET GATE DELAY 0.61 ps f T 178 GHz OFFSET SPACER REDUCES Cov GATE OXIDE (equivalent) 1.9 nm

18. . Deep-submicron CMOS nMOS TRANSISTOR ST at IEDM 2001 Si channel SiO 2 2.75 nm Poly Si Gate L=16 nm SiO 2 CMOS technology still used below 0.02 µm -->some incredulity

19. . ST 80nm ‘SON’ MOSFET 20nm Si on 20nm SiGe on Si BULK SiGe --> TUNNEL = ‘NOTHING’ SELECTIVE ETCHING of SiGe (30%) BURIED ISOLATION of CHANNEL CAN MAKE GATE OX 1.2 nm on 5 nm Si ‘cap’ GATE OXIDE 3 nm

20. . sub - 70 nm SHORT COURSE Yuan TAUR MOSFET TRANSISTORS THIN Si BETTER NO HALO NEEDED

21. . TRANSISTOR SCALING INCREASE in POWER SEVERE LIMITATION COST of PROCESS DEVELOPMENT COST of SINGLE FOUNDRY > 2 G$ TOO LARGE VOLUME ?

22. . + POWER DISSIPATION PROCESSORS NEED COOLING ALICE1 PIXEL CHIP 2.7 cm 2 USES 0.6 to 0.9 W + 0.3 W cm - 2 PIXELS vs Si MICROSTRIP ~3 kW m - 2 vs 0.2 - 0.6 kW m - 2 CRYOGENIC OPERATION ?

23. . PIXEL readout relies on Deep-submicron CMOS Component density + 6 to 9 levels of interconnect 3 metals shown length.35 µm poly Si gate Pixel chips at CERN now 0.25 µm FUNCTIONS SPEED LOW NOISE LOW POWER

24. . DESIGN for PARTICLE PHYSICS at CERN EXAMPLE : PHOTON COUNTING PIXELS COMPLICATED CHIP 0.25 µm CMOS + BUMP-BONDED SENSOR

25. . HYBRID Si PIXEL SENSOR READOUT ELECTRONICS Si SENSOR MATRIX TRUE 2 - D BUMPS +

26. . A LICE1 RESULTS (prelim) THRESHOLD MINIMUM VALUE ~800 e - with SENSOR ~1000 e - NOISE~ 150 e - rms THRESHOLD SPREAD 150 e - rms COMPATIBLE with NOISE TIMEWALK <25 ns 200 e - above threshold DC LEAKAGE CURRENT TOLERATES 200 nA / pixel --> 0.5 - 1 mA cm - 2 RADHARD LAYOUT WORKS UP TO 100 Mrad

27. . Photon Counting Chip CERN Amplifier-Shaper 1 µm SACMOS Comparator 3-bit adjust 16 bit counter common electronic shutter Dark current compensation per column 10 nA Readout 384 µs PCC1 64 x 64 PIXELS 170µm x 170 µm 1997

28. . Photon Counting Chip CERN 15 - bit COUNTER STATIC LOGIC 170µm x 170 µm THRESHOLD ADJUST using 3 bit TRIM Bumpbonding Si or GaAs sensor 400 transistors

29. . Photon Counting Chip CERN 5.9 keV : SOURCE 55 Fe EFFECT FLAT FIELD CORRECTION Compensation for inhomogeneity : source geometry pixel size, window absorption, etc low energy improves contrast

30. . Photon Counting Chip CERN 150 ns PEAKING TIME (linear < 0.4 MHz) HIGH COUNT RATE ~ 10 9 s - 1 cm - 2 Maximum occupancy ~ 50% ELECTRONIC NOISE ~170 e - rms DARK CURRENT COMPENSATION 10 nA / pixel 30 µA cm - 2 TEST SIGNAL INDIVIDUAL PIXELS MASKING of BAD PIXELS THRESHOLD ADJUSTABLE DISTRIBUTION ~120 e - rms ALLOWS LOW THRESHOLD ~1400 e - 5 keV READOUT TIME 384 µs per CHIP SUMMARY

31. . Photon Counting Chip CERN CELL 55µm x 55µm 504 TRANSISTORS 2nd GENERATION Medipix Collaboration + and - polarity0.25 µm CMOS dark current compensation per pixel window discriminator with 3-bit adjusts linear range 80 000 e - 13 bit counter + overflow STATIC LOGIC count rate ~ 10 11 cm -2

32. . PHOTON COUNTING IMAGER WINDOW DISCRIMINATOR ANALOG OUTPUT SIGNAL 17200 e - UPPER COMPARATOR 16400 and LOWER 6300 e -

33. . RADIATION HARDNESS FOUND WAY TO GET 1-10 MGy for TRANSISTOR CIRCUITS IMAGERS ??

34. . RADIATION EFFECTS GATE THRESHOLD SHIFT ionization in gate oxide SOURCE-DRAIN LEAKAGE ionization in field oxide HEAVY IONIZATION EFFECTS SINGLE EVENT EFFECTS ‘SEE’ LATCH-UP GATE RUPTURE MEMORY UPSET, etc.

35. . GATE THRESHOLD SHIFT TUNNELING in THIN LAYER NO CHARGING CLOSE TO INTERFACE

36. . GATE THRESHOLD SHIFT N. SAKS cs. IEEE NS 31(1984) 1249 A to D measurements at CERN 1995- 2000 ~ 1/t ox 2 ~ 1/t ox 3

37. . MOS TRANSISTOR AFTER IRRADIATION NORMAL CURRENT FIELD DRAIN SOURCE ACTIVE REGION LEAKAGE CURRENTS PASSING UNDER BIRD’S BEAKS GATE poly-Si

38. . EDGE LEAKAGE N-MOS CURRENT FROM SOURCE TO DRAIN PASSES UNDER FIELD OXIDE, TRANSISTOR CANNOT BE TURNED OFF

39. . ENCLOSED TRANSISTORS RADIATION TOLERANT BY LAYOUT ONLY SMALL PENALTY IN DEEP SUBMICRON OLD APPROACH (RCA ~1975) N-MOS NEEDS P + GUARD RING FOR SEPARATION SECTION VIEW N-MOSP-MOS

40. . SENSORS at IEDM 2001 MANY TYPES PRESENTED eg SENSOR for CAR TYRE PRESSURE CMOS IMAGERS (also at ISSCC) METAL PLATE as e-GENERATOR for ION IMAGING CCD with MHz 'FRAME-RATE' 4 STORAGE LOCATIONS : ISIS (at ISSCC --> 100) ALTERNATIVE MIT USES BACKSIDE + STORAGE IN FRONT STRUCTURES 512 x 512 96x96 superpixels 8 subpixels -> 12 µm pitch has built-in shutter SOME FUNCTIONS CAN BE MADE in CCD just like in 'our' PIXEL DETECTORS CCD NOW COMPETITIVE due to CAMERAS

41. . SILICON TECHNOLOGY VERY FAST DIODES FOR HIGH FREQUENCY FIBER OPTICS

42. . FAST DIODE IBM : Si on SOI Fast Fourier Transform VERTICAL TRENCHES

43. . CCD IMAGING MULTIPLE FRAMES (4-100) HIGH SPEED (µs) 2 EXAMPLES

44. . CCD with ~1 MHz MULTIPLE FRAME STORAGE FIRST TRY with ‘EXISTING’ CCD USE SUBSET of SENSITIVE PIXELS USE OTHERS for STORAGE

45. . Dipl.-Ing (FH) Dirk Poggemann Fachhochschule Osnabrück Fachbereich Elektrotechnik & Informatik © 2001 Fachhochschule Osnabrück Entwicklung eines In-situ Storage Image Sensors (ISIS) für ein Hochgeschwindigkeitskamerasystem Osnabrück - Philips - Shimadzu- U. Osaka In-situ Storage Image Sensor (ISIS) for High Speed Camera Dipl.-Ing. (FH) Dirk Poggemann Forschungsschwerpunkt “Intelligente Sensorsysteme” (ISYS) Fachbereich Elektrotechnik & Informatik Fachhochschule Osnabrück

46. . ISIS V1 LOWER LEFT CORNER CCD METAL + OPEN PIXELS Dipl.-Ing (FH) Dirk Poggemann Fachhochschule Osnabrück Fachbereich Elektrotechnik & Informatik © 2001 Fachhochschule Osnabrück Entwicklung eines In-situ Storage Image Sensors (ISIS) für ein Hochgeschwindigkeitskamerasystem IMAGE BEFORE SORTING 3% FILL-FACTOR

47. . CCD 17 FRAMES MECHANICAL SHUTTER DURING READOUT

48. . CCD 17 FRAMES NEEDS RE-ORDERING AFTER READOUT

49. . IMPROVED CCD : ISIS V2 Horizontales Ausleseregister Lichtempfindliches Pixel Abgedecktes Speicherpixel 103 STORAGE PIXELS OVERWRITE (DRAIN) PIXEL (ALL UNDER METAL) LIGHT SENSITIVE ELEMENTS (LARGE, OPEN)

50. . IMPROVED CCD : ISIS V2 FILL FACTOR 13 % FULL WELL 40 000 e GREY LEVEL 10 bits ISSCC FEB 2002

51. . IMPROVED CCD : ISIS V2 MANUFACTURED CCD DETAIL of PHOTOSENSITIVE SITES

52. . CCD IMAGING BUILT-IN SHUTTER BLUE/UV-SENSITIVITY by BACKSIDE INCIDENCE

53. . INTEGRATED CCD IMAGER LINCOLN LABS IEDM 2001 (R.Reich et al.) LARGE SIZE : 512 x 96 µm --> ~ 50 mm x 60 mm SUPER PIXEL holds 4 FRAMES FILL FACTOR ~ 100%

54. . CCD IMAGER LINCOLN SUPER PIXEL DESIGN 2x4x12µm 4-phase 96 µm square SPECIAL METALLIZATION NEEDED for MHz BACK-ILLUMINATION Si THICKNESS only 17 µm SHUTTER DIRECTS CHARGE TO SUBPIXEL 17 µm

55. . CCD IMAGER LINCOLN SHUTTER OPERATION SPLIT IN 2 PARTS, DRIFT > 48 µm TOO SLOW for MHz

56. . CCD IMAGER LINCOLN DETAILS SHUTTER IEEE ED 40 (1993) 1231 STEPPED p-BURIED LAYERS using 1.5 MeV IMPLANTS n+ SHUTTER DRAIN SHUTTER 14-18 V

57. . CCD IMAGER LINCOLN SHUTTER EXTINCTION RATIO SHUTTER RISE-FALL TIMES 17 µm Si 25 µm Si ~ 50 ns

58. . CCD IMAGER LINCOLN READOUT CLOCK CYCLES CELL

59. . 512x512 CCD LINCOLN 4 FRAMES :1x 40 ns PULSED LASER 460nm FILTER 550 nm INTEGRATION TIME 2 ms (EXTINCTION RATIO) 4 FRAMES : CONTINUOUS 40 ns SHUTTER OPEN 4 FRAMES 4x 520 ns + 100 ns 1.612 MHz EFFECTIVE OPEN 350 ns CLOSE 150 ns

60. . 512x512 CCD LINCOLN TIMING DIAGRAM TEST 1.612 MHz EFFECTIVE RATE

61. . 512x512 CCD LINCOLN DETAIL METALLIZATION NEEDED for MHz CLOCK SPEED METAL instead of POLY

62. . MONOLITHIC CMOS IMAGERS 'ACTIVE' CIRCUIT in PIXEL at least 1 TRANSISTOR (E. Fossum) USUALLY 'SIMPLE' INTEGRATOR MORE FLEXIBILITY for USER than CCD SOLUTIONS for LARGE DYNAMIC RANGE LOGARITHMIC CHARGE STORAGE ADAPTED INTEGRATION TIME LESS FLEXIBILITY in PROCESSING CMOS FOUNDRY LINES 1000 WAFERS/DAY IMAGERS MAY NEED SPECIAL SUBSTRATES HYBRID CMOS IMAGING ALTERNATIVE

63. . CMOS LARGE DYNAMIC RANGE POTENTIALLY 138 dB IRST Trento SINGLE-PIXEL INTEGRATION ADAPTED TO ILLUMINATION FILL FACTOR 11% TOTAL PIXEL 25 µm x 25 µm 24 transistors COMMUTATION TIME in ANALOG MEMORY or INT. CHARGE

64. . IEDM 2001 IMPRESSIONS REDUCED ATTENDANCE : 970 instead of usual 1800 - 2200 41 SESSIONS a.m. 6, p.m. 7 papers ALL PAPERS 25 min (ISSCC 30’ or 15’ in 26 sessions) strong selection, many time slots not filled 2 SHORT COURSES Sunday 2 Dec 1. TECHNOLOGY for sub-70 nm 2. ADVANCEDE MEMORY TECHN & ARCHITECTURE more popular INDUSTRY MOVEMENTS : e.g. PHILIPS RESEARCH --> IMEC CONCENTRATIONS in IMAGING

65. . CONCLUSION ACCELERATION of SCALING COMPARED to ROADMAP ENORMOUS PROGRESS in ONE YEAR RESEARCH in INDUSTRY NOT MUCH AFFECTED BY DOWNTURN COMPLICATED TECHNOLOGIES ECONOMICS MAKE COMPLICATION ACCEPTABLE --> SOI, SON etc SYSTEM-on-a-CHIP with RF etc SENSORS : both CCD and CMOS