1. Introduction to Experiment 6 Internal FPGA Memories, Pseudo Random Number Generator, Advanced Testbenches ECE 448 Spring 2009

2. 2ECE 448 – FPGA and ASIC Design with VHDL Sources Lecture 14 Xilinx FPGA Memories Lecture 11 Advanced Testbenches P. Chu, FPGA Prototyping by VHDL Examples Chapter 11, Xilinx Spartan-3 Specific Memory Sundar Rajan, Essential VHDL: RTL Synthesis Done Right Chapter 14, starting from “Design Verification” (handout distributed in class)

3. 3ECE 448 – FPGA and ASIC Design with VHDL Sources XAPP463 Using Block RAM in Spartan-3 Generation FPGAs Google search: XAPP463 XAPP464 Using Look-Up Tables as Distributed RAM in Spartan-3 Generation FPGAs Google search: XAPP464 XST User Guide, Section: Coding Techniques Google search: XST User Guide (PDF) http://www.xilinx.com/itp/xilinx4/data/docs/xst/hdlcode.htmlhttp://www.xilinx.com/itp/xilinx4/data/docs/xst/hdlcode.html (HTML) ISE In-Depth Tutorial, Section: Creating a CORE Generator Module Google search: ISE In-Depth Tutorial

4. Addr Din Dout PRNG SORTING/ EDIT RAM CONTROL INPUT INTERFACE OUTPUT INTERFACE CURRENT ADDRES joystick Two 7-segment displays 8 LEDs Curr_Addr from CONTROL

5. Task 1 – Browsing Mode 00 01 02 03 04 05 …. FA FB FC FD FE FF 00 01 02 03 04 05 …. FA FB FC FD FE FF AddressData Current Address Two 7-Segment Displays (in hexadecimal notation) Joystick up = Increment Address Joystick down = Decrement Address 8 LEDs (in binary notation) Value at Current Address 256x8 RAM

6. Task 2 – Edit Mode 00 01 02 03 04 05 …. FA FB FC FD FE FF 00 01 02 03 04 05=>06 …. FA FB FC FD FE FF AddressData Current Address Two 7-Segment Displays (in hexadecimal notation) Joystick up = Increment Address Joystick down = Decrement Address 8 LEDs (in binary notation) Value at Current Address 256x8 RAM Joystick Enter = Edit Joystick up = Increment Data Joystick down = Decrement Data Joystick Enter = Approve

7. Task 3 – Initialize 00 01 02 03 04 05 …. FA FB FC FD FE FF 25 87 94 26 B5 C6 …. 7A 5B 34 43 89 78 AddressData Joystick Enter = Initialize with Pseudorandom Values 256x8 RAM

8. Pseudo Random Number Generator (PRNG) A pseudorandom number generator (PRNG) is an algorithm for generating a sequence of numbers that approximates the properties of random numbers. The sequence is not truly random in that it is completely determined by a relatively small set of initial values. A PRNG can be started from an arbitrary starting state, using a seed state. It will always produce the same sequence thereafter when initialized with that state. The maximum length of the sequence before it begins to repeat is determined by the size of the state, measured in bits. PRNG Circuit can be constructed from a Linear Feedback Shift Register (LFSR) circuit *from http://en.wikipedia.org/wiki/PRNGhttp://en.wikipedia.org/wiki/PRNG

9. Linear Feedback Shift Register (LFSR) A linear feedback shift register (LFSR) is a shift register whose input bit is a linear function of its previous state. The only linear functions of single bits are xor and inverse-xor; thus it is a shift register whose input bit is driven by the exclusive-or (xor) of some bits of the overall shift register value. *from http://en.wikipedia.org/wiki/LFSRhttp://en.wikipedia.org/wiki/LFSR

10. 8-bit LFSR (Linear Feedback Shift Register) with the period of 2 8 -1 8 R R0R0 R1R1 R2R2 R3R3 R4R4 R5R5 R6R6 R7R7 = D flip-flop with set or reset determining its initial value after “soft” reset Run for 8 clock cycles before using a new output value.

11. Task 4 – Sorting 00 01 02 03 04 05 …. FA FB FC FD FE FF 25 37 44 56 57 78 …. B4 B6 B8 CC D4 FF AddressData Joystick Enter = sorting using one of the following types sorting signed numbers in the descending order sorting signed numbers in the ascending order sorting unsigned numbers in the descending order sorting unsigned numbers in the ascending order Joystick Up changing sorting type 256x8 RAM

12. Task 5 – Advanced Testbench Processes Generating Input Stimuli Design Under Test (DUT) Process Comparing Actual Outputs vs. Expected Outputs Design Correct/Incorrect Yes/No Testvector file(s)

13. Task 5 – Format of an input file number of entries to be sorted (in decimal) empty line numbers to be sorted in the initial order (in the hexadecimal notation, one number per line) empty line numbers after sorting (in the hexadecimal notation, one number per line) 6 B4 89 A3 58 61 78 58 61 78 89 A3 B4

14. Task 6 : Different Memory Types Memory Distributed (MLUT-based) Block RAM-based (BRAM-based) Inferred Memory Manually Using Core Generator

15. Task 7: Dual-port Memory Replace Single-Port RAM with Dual-Port RAM and redesign Sorting Logic accordingly Calculate the gain in terms of - average execution time - smaller resource utilization.

16. Introduction to Core Generator (Hands-on Session)