1. ECE 448 – FPGA and ASIC Design with VHDL Lecture 12 PicoBlaze Overview

2. 2 ECE 448 – FPGA and ASIC Design with VHDL Required reading P. Chu, FPGA Prototyping by VHDL Examples Chapter 14, PicoBlaze Overview Recommended reading K. Chapman, PicoBlaze for Spartan-6, Virtex-6, and 7-Series (KCPSM6)

3. 3 Block diagram of a Single-Purpose Processor (FSMD – Finite State Machine with Datapath) ECE 448 – FPGA and ASIC Design with VHDL ctrl

4. 4 Block diagram of a General-Purpose Processor (Microcontroller) ECE 448 – FPGA and ASIC Design with VHDL

5. 5 PicoBlaze-3

6. PicoBlaze-3 Overview

7. PicoBlaze-6 Overview

8. Size of PicoBlaze-6 in Spartan 6 1.Resource Utilization in CLB Slices ? 2.Number of PicoBlaze-6 cores fitting inside of the Spartan-6 FPGA (XC6SLX16) used in the Nexys3 FPGA board ? Make an educated guess

9. Size of PicoBlaze-6 in Spartan 6 1.Resource Utilization in CLB Slices 26 CLB Slices 1.1% of Spartan-6 used in Nexys3 2.Number of PicoBlaze-6 cores fitting inside of the Spartan-6 FPGA (XC6SLX16) used in the Nexys3 FPGA board 87 PicoBlaze cores

10. Speed of PicoBlaze-6 in Spartan 6 1.Maximum Clock Frequency ? 2.Maximum number of instructions per second ? Make an educated guess

11. Speed of PicoBlaze-6 in Spartan 6 1.Maximum Clock Frequency 105 MHz 2.Maximum number of instructions per second 52.5 millions of instructions per second (MIPS)

12. Register File of PicoBlaze-3 0 1 7 7 7 0 0 0 Address 70 70 70 70 70 16 Registers 8-bit 70 F s0 s1 s2 s3 s4 s5 s6 s7 2 3 4 5 6 7 sF

13. Register File of PicoBlaze-6 Instructions REGBANK A REGBANK B used to switch between banks Only one set of flags Z, C, I Very useful for interrupt service routines

14. Definition of Flags Z = 1 if result = 0 0 otherwise Zero flag - Z zero condition Example* C = 1 if result > 2 8 -1 (for addition) or result < 0 (for subtraction) 0 otherwise *Applies only to addition or subtraction related instructions, refer to the following slides otherwise Carry flag - C overflow, underflow, or various conditions Flags are set or reset after ALU operations

15. 15 Interface of PicoBlaze-3 ECE 448 – FPGA and ASIC Design with VHDL KCPSM = constant (K) coded programmable state machine

16. 16 Interface of PicoBlaze-3 ECE 448 – FPGA and ASIC Design with VHDL NameDirectionSizeFunction clkinput1System clock signal. resetinput1Reset signal. addressoutput12Address of the instruction memory. Specifies address of the instruction to be retrieved. instructioninput18Fetched instruction. port_idoutput8Address of the input or output port. in_portinput8Input data from I/O peripherals. read_strobeoutput1Strobe associated with the input operation. out_portoutput8Output data to I/O peripherals. write_strobeoutput1Strobe associated with the output operation. interruptinput1Interrupt request from I/O peripherals. interrupt_ackoutput1Interrupt acknowledgment to I/O peripherals

17. 17 Interface of PicoBlaze-6 ECE 448 – FPGA and ASIC Design with VHDL

18. 18 Additional Ports of PicoBlaze-6 ECE 448 – FPGA and ASIC Design with VHDL NameDirectionSizeFunction bram_enableoutput1Read enable for the program memory. This signal should be connected to the enable input of the program memory and is used to reduce the power consumption associated with the BRAM(s). k_write_strobeoutput1This output will pulse High for one clock cycle when KCPSM6 executes an ‘OUTPUTK’ instruction and the peripheral logic should capture the data provided on ‘out_port’ into the intended destination defined by the value of ‘port_id[3:0]’. Note that only the lower 4-bits of ‘port_id’ are used during ‘OUTPUTK’. sleepinput1Active High sleep control. When driven High KCPSM6 will complete the current instruction and then enter a sleep mode in which all activity stops. Whilst in the sleep mode all strobes are inactive and the ‘bram_enable’ is Low to disable the program memory resulting in minimum power consumption. All inputs except ‘reset’ are ignored. When ‘sleep’ is returned Low, KCPSM6 resumes execution from the point that it stopped.

19. 19 Generics of PicoBlaze-6 ECE 448 – FPGA and ASIC Design with VHDL NameDefaultRangeFunction hwbuildX”00”X”00”..X”FF”can be used to define any 8-bit value in the range ‘00’ to ‘FF’. It is then possible to load any KCPSM6 register with this value using the ‘HWBUILD sX’ instruction interrupt vector“X3FF”X”00”..X”FFF”When an interrupt occurs (and interrupts are enabled) then KCPSM6 inserts and executes a special form of CALL instruction to a fixed address known as the interrupt vector. By default this address is ‘3FF’ (the last location of a 1K program memory). scratch_pad_ memory_size 6464, 128, 256Size of the scratch pad memory. Increasing the default size to 128 (256) bytes, increases the resource utilization by 2 slices (6 slices).

20. 20 PicoBlaze-6 Instantiation ECE 448 – FPGA and ASIC Design with VHDL

21. 21 ECE 448 – FPGA and ASIC Design with VHDL Development Flow of a System with PicoBlaze