1. ECE 449: Computer Design Lab Coordinator: Kris Gaj TAs: Tuesday session: Pawel Chodowiec Thursday session: Nghi Nguyen

2. Tasks of the course Advanced course on digital system design with VHDL Introduction to FPGA technology Testing equipment - writing VHDL code for synthesis - RTL VHDL - state machines - test benches - hardware: Xilinx FPGAs - software: Aldec simulator Xilinx ISE - oscilloscope - logic analyzer

3. Subset of VHDL used in ECE 449 VHDL model behavioral structural data flowalgorithmic Registers State machines Test benches Required Not required Concurrent statementsSequential statements

4. Structural VHDL component instantiation (port map) component instantiation with generic (generic map, port map) generate scheme for component instantiations (for-generate) Major instructions

5. Data-flow VHDL concurrent signal assignment (  ) conditional concurrent signal assignment (when-else) selected concurrent signal assignment (with-select-when) generate scheme for equations (for-generate) Major instructions Concurrent statements

6. Algorithmic VHDL (subset) process statement (process) sequential signal assignment (  ) Major instructions Sequential statements General Registers if-then-else statement State machines case-when statement Testbenches loops (for-loop, while-loop)

7. Digital system design technologies Microprocessors ASICs FPGAs ECE 445 ECE 442 ECE 447 ECE 586 ECE 680 ECE 681 ECE 645 ECE 681 ECE 645 ECE 449 ECE 511 ECE 611 ECE 431 Computer Organization Digital Computer Design & Interfacing Single Chip Microcomputers Computer Design Lab Digital Circuit Design Microprocessors Advanced Microprocessors VLSI Design Automation Computer Arithmetic Digital Integrated Circuits Physical VLSI Design

8. FPGAs vs. ASICs ASICs FPGAs High performance Off-the-shelf Short time to the market Low development costs Reconfigurability Low power Low cost (but only in high volumes)