1. ECE 448: Spring 11 Lab 3 Part 1 Sequential Logic for Synthesis

2. Introduction: Why are we here? Part 1: Pseudorandom Random Number Generators Part 2: Debouncing Circuit Part 3: Rising Edge Detector Part 4: Counter Part 5: Clock Divider Part 6: Basys II Part 7: FPGA Design Flow based on Aldec Active-HDL Agenda for today

3. Introduction Purpose- Test basic circuits on the Basys II – Counter – Debouncing circuit – Rising edge detector Introduction to Pseudo-Random Number Generator (PRNG) Introduction to FPGA Design Flow based on Aldec Active-HDL

4. Debouncer test Notation: RED – Rising Edge Detector 7-Seg Display Unit 15:87:0 Generic n=8 Counter rst_i step_i clk_i data_o en_i 8 Generic n=8 Counter rst_i step_i clk_i data_o en_i 8 RED button(0) button(2) sw(3:0) zeros(7:4) 8 RED DEBOUNCER button(1) clk_50M clk_1k rst_i

5. Top-level Circuit for Lab 3 Notation: RED – Rising Edge Detector 7-Seg Display Unit 15:87:0 rst_i clk_i data_o en_i 8 PRNG rst_i clk_i data_o en_i 8 RED button(0) button(2) DEBOUNCER clk_50M clk_1k Generic n=8 Counter rst_i

6. Part 1 Pseudo-Random Number Generator

7. PRNG Also known as Deterministic Random Bit Generator (DRBG) Generates a sequence of numbers that approximates the properties of random numbers. The sequence is fully deterministic, i.e., it can be repeated based on an initial state of PRNG. The period of the sequence may be made very large (typically, 2 n -1, where n is an internal state size)

8. PRNG Random Numbers are often important – Testing of VLSI circuits – Cryptography – Monte Carlo simulations – Noise addition – Bit error detection, and many other applications

9. PRNG

10. Block Diagram of Lab 3 PRNG

11. Inputs of XOR gates

12. Three Initialization Options Option 1 (required): Initialization to ALL ONES, using the signal SET common to all shift registers (connected to rst_i). Option 2 (required): Initialization to ALL ONES by shifting '1’ to all shift registers for 6 clock cycles after reset. Option 3: (bonus): Initialization to arbitrary value, by shifting in internal state serially, using special input sin, one bit per clock cycle.

13. PRNG Test Vectors Clock CycleOutput 1FF 274 3BD 467 5EA 6AE 74E 85B 9 6A 1062 Clock CycleOutput 11D9 1231 1387 1438 1595 1619 175c 18CE 197E 2052

14. Part 2 Debouncing Circuit

15. Debouncer Capacitance in the button and contacts “bouncing” causes spurs that cause false positives. A debouncing circuit removes these spurs.

16. Debouncer When the first change is detected, we ignore all subsequent changes for some period of time, preferably until all of the bouncing would have occurred. This is usually on the order of ms.

17. Debouncer reset input clk output

18. Debouncer

19. Part 3 Rising Edge Detector

20. Turn a step function into an impulse Allows a step to run a circuit for only one clock cycle Can also be used to cross clock domains Rising Edge Detector

21. clk_i data_i data_o data_i clk_i data_o rising edge detector

22. Part 4 Counter

23. Count whenever enable signal is high Synchronous reset Data out is valid after one clock cycle Increment step size is configurable Why use a generic? – Generics make circuits reusable

24. Counter Generic n Counter rst_i step_i clk_i data_o en_i n n

25. Counter Register 0 1 step_i en_iclk_i data_o n n n n rst_i

26. Part 5 Clock Divider

28. Counter = c n rst_i en clk_i clk_o data_o en_i step_i 1 n

29. Part 6 Basys II

31. Switches (8) Buttons (4) 7 Segment Displays (4) VGA connector ON/OFF Switch Expansion ports LEDs (8)

32. Basys 2 I/O Circuits

33. Seven Segment Display By lighting different combinations of LEDs, different figures appear For Instance CA, CB, CC make ‘7’ Common anode means that writing a ‘0’ to CA- DP illuminates the led, where a ‘1’ turns it off

34. Seven Segment Display SSRegCtrl has a 16 bit input that is divided into four 4- bit digits AN(0:3) select which 7 segment display to output to Digilent recommends a digit period of between 1kHz and 60Hz

35. Part 7 FPGA Design Flow based on Aldec Active-HDL

36. FPGA Design process (1) Design and implement a simple unit permitting to speed up encryption with RC5-similar cipher with fixed key set on 8031 microcontroller. Unlike in the experiment 5, this time your unit has to be able to perform an encryption algorithm by itself, executing 32 rounds….. Library IEEE; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity RC5_core is port( clock, reset, encr_decr: in std_logic; data_input: in std_logic_vector(31 downto 0); data_output: out std_logic_vector(31 downto 0); out_full: in std_logic; key_input: in std_logic_vector(31 downto 0); key_read: out std_logic; ); end AES_core; Specification (Lab Assignments) VHDL description (Your Source Files) Functional simulation Post-synthesis simulation Synthesis On-paper hardware design (Block diagram & ASM chart)

37. FPGA Design process (2) Implementation Configuration Timing simulation On chip testing

38. Design Process control from Active-HDL