1. Developing fast clock source with deterministic jitter Midterm review Yulia Okunev Supervisor -Yossi Hipsh HS-DSL Laboratory, Dept. of Electrical Engineering Technion – Israel Institute of Technology 20.05.2014

2. 2 Background In this project I designed fast clock source with deterministic jitter for high speed phenomena experiment. Jitter [1] is the deviation of a periodic signal, in this case, clock source, from its ideal period. Or in other words the period frequency displacement of the signal from its ideal location. System overview: Pulse generator is used to produce electrical input signal. This clock signal will be divided to 8 channels. Each signal passes through delays array and combined in the output. Using Scope we can measure the system output.

3. Project Top Block diagram 3 Pulse Generat or 0.5nSec Clock Signal divider delays array Clock Signal combiner Built-In-Test

4. Solution algorithm 4 Passive delays array: We created different length transmission lines which causes the signal to delay respectively to the line length. The lines will be printed on the top layer of the PCB (microstrip) Passive clock divider/combiner: We created divider (combiner) for the clock signal using resistor divider (combiner)

5. Theory and calculations

6. 6 Transmission lines Parameters 8 high speed lines impedance 50Ω, on top layer – microstrip lines. The delay delta between each two lines is approximately 725psec To create between each two transmission lines the required is: 0.12m We chose to be smaller than the input signal period. This way the input signal contains the divided signal in one period as shown:

7. 7 Transmission lines Parameters-cont.. We can control by choosing different We can reduce the propagation time in each line by reducing it’s length We can increase the propagation time in each line by increasing it’s length

8. 8 Schematic Passive delays array Passive clock dividerPassive clock combiner Junction model Passive clock divider Passive clock combiner Is a mirror image of Junction model

9. 9 Passive delays array Transmission lines Parameters: Transmission lines length to create equal between each two signals (ideal clock) are : 0.12m, 0.24m, 0.36m, 0.48m,0.60m,0.72m, 0.84m, 0.96m In order to create Jitter, we will use non ideal values for lines length : Transmission lines length to create jitter are: 0.12m, 0.22m, 0.38m, 0.48m,0.60m,0.70m, 0.84m, 0.95m Input signal Ideal output Jitter in output

10. 10 Junction model In simplified way we can think the junction is just a connection between 3 resistors. But each line should be modeled as a transmission line The calculation is as follow:

11. 11 Junction Schematic-Zoom in

12. Simulation

13. 13 Simulation Input signal to output signal Input signal data: T=30 nsec Rise time=150 psec Fall time=150 psec Time the signal is high =50 psec Amplitude=926.87mV Output signal data: Amplitude=15.11mV Attenuation between Input signal and Output signal: 35.7dB This is sufficient for our needs

14. 14 Simulation Output signal to undesired output signal Zoom in on the output Minimal signal amplitude: 11.67mV Maximal noise amplitude: 4.04mV Attenuation between Output signal and undesired signal: 9.2dB This is sufficient for our needs

15. 15 Simulation output signal Transmission lines length to create equal between each two signals: 0.12m, 0.24m, 0.36m, 0.48m,0.60m 0.72m, 0.84m, 0.96m Zoom in on the output Maximal signal amplitude: 13.022mV Minimal noise amplitude: 11.283mV Delta: 1.25dB This is sufficient for our needs

16. 16 Simulation output signal Transmission lines length to create jitter: 0.12m, 0.22m, 0.38m, 0.48m, 0.60m,0.70m, 0.84m, 0.95m As we can see from the simulation larger between two lines causes larger and vice versa Maximal signal amplitude: 13.022mV Minimal noise amplitude: 9.522mV Delta: 2.72dB This is sufficient for our needs

17. Schematic

18. 18 Schematic

19. Board stuck-up and Junction Layout

20. 20 Stuck-up

21. 21 Transmission line calculations

22. 22 Components Resistors: Value: 16.7, 50 ohm. Size: 0603 Power consumption: 0.125W (maximal power in circuit: ) Connectors: BNC

23. Project Gantt 23 StatusWeekExamination and purchase of the required components Done4Examine the performance of the chosen power splitter\combiner Done4Examine the physical ability to integrate this component in a printed circuit. Done5Getting price and delivery time suggestion Done5Examination of the scope measuring capability to determine whether we need microwave amplifier Done6Preliminary high level design : Examination of the required support components such as: amplifiers (if needed), connectors, build-in test components etc.

24. Project Gantt 24 WeekSystem design, manufacture and verification Done7Noise considerations (and SNR) in the system Done8-9Simulation using Sig-Explorer. (Examination of system performance) 10-11Built-In-Test and PCB design 12Final PCB review before manufacture --Once boards will be manufactured-visual inspection and electrical examination

25. Junction model Further details

26. 26 Junction model In simplified way we can think the junction is just a connection between 3 resistors. But each line should be modeled as a transmission line The calculation is as follow:

27. 27 Impedance calculation In order to have 66.7 impedance we need the line width to be 22MIL In order to enter to the junction with thin line we will narrow the line close to the junction and expand the line further away from the junction to fit horizontally to a 0603 resistor.

28. 28 Impedance calculation-cont.. 22.5-7.5=15 mil 22.5+7.5=30 mil 24 mil

29. 29 Junction layout 12 mil

30. 30 Summary – Junction model

31. 31 Reference [1] http://www.antelopeaudio.com/ [2] http://il.farnell.com/

32. 32 Thank you Yulia Okunev