1. 1 Pulse Generator High Speed Digital Systems Lab Semestrial project – Winter 2007/08 Final Presentation Instructor: Yossi Hipsh Students: Lior Shkolnitsky, Yevgeniy Lobanov

2. 2 Topics The Challenge Overview The Challenge Overview I/O scheme I/O scheme Block Diagram Block Diagram General View General View Electrical Scheme Electrical Scheme Stack Layout Stack Layout Bill Of Materials Bill Of Materials Measurements Measurements General General Set Up Set Up Results Results

3. 3 The Challenge Overview The Challenge Overview The main goal is to design an Adjustable Pulse Generator. The main goal is to design an Adjustable Pulse Generator. This Generator will be integrated into an existing lab experiment, that teaches about High Speed Systems Phenomena: reflections, skew, jitter, etc. This Generator will be integrated into an existing lab experiment, that teaches about High Speed Systems Phenomena: reflections, skew, jitter, etc. The Generator will create a very short (0.5-1 nsec) and a longer (10-13 nsec) pulse signal into transmission line. The Generator will create a very short (0.5-1 nsec) and a longer (10-13 nsec) pulse signal into transmission line.

4. 4 I/O scheme Adjustable Pulse Generator Power supply Pulse width selection Short pulse Long pulse

5. 5 Power Supply 6 V 10 nsec 0.5-1 nsec 3.3 V 700 mA Block Diagram Splitter AND Manual Selector Adjustable Delay Adjustable Delay 1-shot Translator TTL Diff LVPECL 100 nsec 10 nsec Translator TTL Diff LVPECL 1.3V Voltage Regulator 3.3V Voltage Regulator Oscillator

6. 6 Splitter AND Adjustabl e Delay Adj. Delay 1 shot Transl ator TT L Diff LVPE CL Translat. TTL Diff LVPE CL Osc. General View Each Switch – 16 states Each Delay Unit – 8 (of 10) wires of control

7. 7 Electrical Scheme (1/2)

8. 8 Electrical Scheme (2/2) All The 50 ohm Resistors – Close to receiver Each Red line –– fast signal – Upper Layer Bypass Capacitors – Close to the Power Pins All 4 lines have the same length

9. 9 Stack Layout SIGNAL FR 4 GND Vcc (ECL) = 3.3 V GND 2 FR 4 each metal layer – Copper each dielectric layer: er=4.3 Control FR 4 Vtt = 1.3 V FR 4 250um thickness 50um thickness

10. 10 Bill Of Materials # NamePart NumberQuantityIn lab 1Voltage Regulator LM1085 – 3.3V1Yes LM1085 – ADJ1Yes 210MHz Oscillator CO1025-10-3.31Yes 3Flip Flop (One Shot) MC74LCX74DG1No 4Splitter (Fan Out Buffer) MPC945511No 5TTL to LV PECL Translator MC100EPT202No 6Adjustable Delay MC100EP1952No 7AND Gate MC100EP051No 8Pair of Manual Selectors PA-G-A-3-2-002No 9Connector for Manual Selector C2KF-P1094No 10Resistors /Capacitors/ Diodes Yes Appendix 1 (click to jump)

11. 11 Measurements We did measurements, as if after production. Those measurements are for validating the generator’s functionality, and for debug. The Pulse Generator Device was simulating the designed Pulse Generator Card. The Pulse Generator sent a pulse, similar to the expected pulse from the Card. General

12. 12 Measurements Instruments used: Pulse Generator – HP 8133A – emulated the DUT 50 GHz Sampling Scope – HP 83480A, 54752A Attenuators – 6dB, 18 GHz BW Set Up Pulse Generator Signal Trigger Scope

13. 13 Measurements All the Measurements may be observed right now in lab…

14. 14 Measurements Measured Parameters: Timing: Pulse width 475 psec Time jitter (p-p) 11.6 psec Rise time, fall time44.4, 43.6 psec Voltage Pulse amplitude381 mV Voltage jitter (p-p) 1.3 mV Results (1/4)

15. 15 Scope screenshot, started to capture: Measurements Results (2/4)

16. 16 Scope screenshot, after 1 hour of capture: ה -jitter גדל Measurements Measurements Results (3/4)

17. 17 Zoom on rising and falling edges: Measurements Results (4/4)

18. 18 Questions / Answers Thank you!

19. 19 Appendix 1 Resis. [Ω] RoleQuan. 150Termination to Vtt10 25Voltage Regulator for Vtt1 3121Voltage Regulator for Vtt1 41000Switches protection2 Resistors Capacitors Capac. [μF]RoleQuan. 110Voltage Regulators4 20.1Bypass Capacitors7 30.001Bypass Capacitors7 4TBDMonostable feedback1 Go back…Diodes Part No.RoleQuan. 11N4002Protection of the PS and Voltage Regulators 3

20. 20 Future Plans – Time Table End date 24/131/17/214/223/2 Making the board Building the prototype The test setup – designing, debugging Writing the report Final Presentation

21. 21 Time Table Task \ Week 1234567891011121314 Exploring the problem 22- 10 Definition presentation 22- 11 Block diagram consolidation Finding suitable components Designing the board Design presentation 19- 12 Ordering components and board Writing the booklet Designing a test setup Building the project 15- 01 Building the test setup Test and Debug Final presentation 30- 01

22. 22 The Signal 0.5 nsec 2V

23. 23 Input Calculation For example – 3 nsec delay 10-3= 7 nsec (shift of the left delay unit) 7 nsec – 1010111100 (700*10psec) 1010 __ 1111__00 Left switch – AF Right switch - 00