1. Review of Digital Logic Design Concepts OR: What I Need to Know from Digital Logic Design (EEL3705)

2. Basic Digital Logic Gates A Review

3. Digital (Positive) Logic Logic Level High –1 or ONE or HIGH or H or +Vdd or yes or ON or True Logic Level Low –0 or ZERO or LOW or L or GND or no or OFF or False 0 1

4. Definitions Assert –A control signal is asserted when the action control by the signal is being done. –Ex: Assume a control signal labeled en en is asserted when en is high Active low signal –A signal that is asserted when it is a logic level low. Active high signal –A signal that is asserted when it is a logic level high.

5. Buffer or Driver AY 00 11 Symbol Equation Truth Table AY

6. Tri-State Buffer or Driver AEY 00Z 010 10Z 111 Symbol Equation Truth Table AY E Z = high impedance

7. NOT (Inverter) GATE AY 01 10 Symbol Equation Truth Table

8. AND GATE Symbol Equation ABY 000 010 100 111 Truth Table

9. NAND GATE Symbol Equation Truth Table ABY 001 011 101 110

10. OR GATE Symbol Equation Truth Table ABY 000 011 101 111

11. NOR GATE Symbol Equation Truth Table ABY 001 010 100 110

12. XOR GATE Symbol Equation Truth Table ABY 000 011 101 110

13. XNOR GATE Symbol Equation Truth Table Equivalence Function ABY 001 010 100 111

14. Digital Logic Types Combinatorial Logic Circuits –No Memory (or Registers) Sequential Logic Circuits –Memory (or Registers) Asynchronous Logic Circuits –No common clock Synchronous Logic Circuits –Common clock Synchronous Sequential Circuits

15. Memory Storage Registers Latches and Flip-Flops

16. D-Latch with (P)reset DE PreRstQ n+1 dd100 dd011 d011QnQn 01110 11111 Symbol Equation (level clock)Truth Table When Pre/SET (Preset) is asserted, Q → 1 immediately. When Rst/CLR (Reset) is asserted, Q → 0 immediately. When neither SET nor CLR is asserted, Q → D (data) when E (enable) is asserted; Maintains previous value otherwise. d = “don’t care”

17. D Flip-Flop Positive Edge Triggered DClk PreRstQ n+1 dd100 dd011 d011QnQn d111QnQn 0110 1111 Symbol Equation (rising clock) Truth Table Q changes to D on rising edge of Clk

18. Basic Memory Devices Registers –Basic –Multi-Function (Shift, Load, Hold,...) Counters –Asynchronous –Synchronous –Up / Down –Modulo Counters

19. Finite State Machines

20. Finite State Machines (FSMs) Three basic types 1. Moore FSM 2. Mealy FSM 3. Mealy-Moore FSM

21. Moore FSM General Block Diagram Input Vector Output Vector Next State Present State Feedback Path CL= Combinational Logic Cloud Reg= D Registers Clock Reset

22. Moore FSM State Equations Input Vector Output Vector Next State Present State Feedback Path Clock Reset State Equations

23. Mealy FSM State Equations Input Vector Output Vector Next State Present State Feedback Path

24. Mealy-Moore FSM State Equations Input Vector Next State Present State Mealy Outputs Moore Outputs

25. State Diagrams

26. State Bubble

27. State Bubble Example Unconditional Transition State name = S0 State value = 00 Y = 0 for this state

28. FSM Example

29. Example 2– 2-bit Up Counter State Diagram Clock is implied

30. Example – 2-bit Up Counter State Table psnsy S0S10 S21 S32 S03 S0 = 00 S1 = 01 S2 = 10 S3 = 11 Let Let S0 = reset state State Value Assignment Output Vector

31. Example – 2-bit Up Counter Truth Table ps1ps0ns1ns0y1y0 000100 011001 101110 110011

32. Example – 2-bit Up Counter Excitation Equations

33. Recall Moore FSM Input Vector Output Vector Next State Present State Feedback Path Clock Reset State Equations

34. Logic Diagram F Logic H Logic Reg Block Y Vector No X Vector in this Example No H Logic needed

35. 2-bit Counter in 68HC11 Assembly L0: LDAA #$00 ; Reset A with 0 L1: INCA ; A=A+1 CMPA #$03 ; Is A=3? BNE L1 ; No. Increment A JMP L0 ; Yes, Reset A to 0