1. © Chandu Visweswariah, 2004New Challenges in IC Design1 New Challenges in IC Design … with a focus on variability … SBCCI 2004 Panel Discussion Chandu Visweswariah Research Staff Member IBM Thomas J. Watson Research Center Yorktown Heights, NY

2. © Chandu Visweswariah, 2004New Challenges in IC Design2 Where will performance come from? Technology scaling –will require ever-more exotic materials and tricks –will yield diminishing performance enhancements Performance will come from –multiple processors/cores –packaging options (3D ICs, silicon carrier) –better memory hierarchies –better tools –better compilers

3. © Chandu Visweswariah, 2004New Challenges in IC Design3 Outline Challenge #1: migrate from corner-based timing to statistical timing Challenge #2: adopt robust design methodologies and practices Challenge #3: simultaneous timing and (leakage) power sign-off Challenge #4: stop targeting worst-case design; rather, design adaptive circuits that can recover from low-probability problems

4. © Chandu Visweswariah, 2004New Challenges in IC Design4 The march of technology Performance Technology generation Is this worth a huge investment?

5. © Chandu Visweswariah, 2004New Challenges in IC Design5 1: Corner-based vs. statistical timing

6. © Chandu Visweswariah, 2004New Challenges in IC Design6 Benefit of statistical timing n = # independent sources of variation (say 9)  = total variability in critical path delay (say 5%) Fractional increase in frequency with a 3  sign-off instead of 3  n sign-off Assumes sources of variation are roughly equally significant

7. © Chandu Visweswariah, 2004New Challenges in IC Design7 Corner-based vs. statistical

8. © Chandu Visweswariah, 2004New Challenges in IC Design8 2: Robustness Reduce sensitivity of performance to variations; examples: –N/P mistracking: avoid too many tall N or tall P stacks in critical paths –Gate/wire mistracking: use equal fractions of gates and wires in data and clock paths –ACLV/OCV: use compact layouts so that capturing and launching paths are close by –V t mistracking: use equal fractions of low V t transistors in critical data and clock paths

9. © Chandu Visweswariah, 2004New Challenges in IC Design9 Q&A Q: Where will the models come from? A: IDMs have an advantage Q: What will the models look like? A: Analytic forms are more conducive than table-based delay modeling formats Q: Can timers handle the capacity? A: Yes; 2.1M gate design timed in 69 minutes with 10.9 GB memory; 1.1M gate design timed in 110 minutes (dominated by load time) with 4.3 GB memory Q: How will it be phased in? A: (a) true 3  sign-off (b) implicit robustness credit (c) explicit robustness targeting (d) at-speed test for yield/speed tradeoffs

10. © Chandu Visweswariah, 2004New Challenges in IC Design10 BEOL early-mode variability on ASIC part Pessimism reduction -3  slack: -162 ps Exhaustive corner analysis: -225 ps *Early mode; variability in 7 metal levels

11. © Chandu Visweswariah, 2004New Challenges in IC Design11 Too leaky 3: Simultaneous power/timing sign-off Too slow Probability VtVt Good chips

12. © Chandu Visweswariah, 2004New Challenges in IC Design12 4: Adaptive circuits Key idea: we are penalizing performance by covering low-probability problems Instead, recover from the low-probability problems adaptively –sensor circuits: to sense temperature, a late signal, a wrong logical value, V t, a mistracking situation –actuator circuits: to change back-gate bias, change V dd, repeat a computation, gate the clock, throttle instruction issue Adaptive circuits protect against static variability, dynamic variability and single-event upsets A wealth of design, CAD, methodology and verification problems suggest themselves!

13. © Chandu Visweswariah, 2004New Challenges in IC Design13 Conclusion Variability is causing a number of problems –leakage power –timing closure –excessive pessimism –worst-case design kills scaling benefit Paradigm shifts are periods of opportunity: One person’s headache is another’s windfall!