1. Lecture #26 Page 1 ECE 4110– Sequential Logic Design Lecture #26 Agenda 1.State Encoding 2.Pipelined Outputs 3.Asynchronous Inputs Announcements 1.n/a

2. Lecture #26 Page 2 State Encoding State Variable Encoding - we can decide how we encode our state variables - there are advantages/disadvantages to different techniques Binary Encoding - straight encoding of states S0 = “00” S1 = “01” S2 = “10” S3 = “11” - for n states, there are log(n)/log(2) flip-flops needed - this gives the Least # of Flip-Flops - Good for “Area” constrained designs - Drawbacks:- multiple bits switch at the same time = Increased Noise & Power - the Next State Logic “F” is multi-level = Increased Power and Reduced Speed

3. Lecture #26 Page 3 State Encoding Gray-Code Encoding - encoding using a gray code where only one bits switches at a time S0 = “00” S1 = “01” S2 = “11” S3 = “10” - for n states, there are log(n)/log(2) flip-flops needed - this gives low Power and Noise due to only one bit switching - Good for “Power/Noise” constrained designs - Drawbacks:- the Next State Logic “F” is multi-level = Increased Power and Reduced Speed

4. Lecture #26 Page 4 State Encoding One-Hot Encoding - encoding one flip-flop for each state S0 = “0001” S1 = “0010” S2 = “0100” S3 = “1000” - for n states, there are n flip-flops needed - the combination logic for F is one level (i.e., a Decoder) - Good for Speed - Especially good for FPGA due to “Programmable Logic Block” - Drawbacks:- takes more area

5. Lecture #26 Page 5 State Encoding State Encoding Trade-Offs - We typically trade off Speed, Area, and Power speed power area One-Hot BinaryGray

6. Lecture #26 Page 6 Pipelined Outputs Pipelined Outputs - Having combinational logic drive outputs can lead to: - multiple delay paths through the logic - potential for glitches - Both reduce the speed at which the system clock can be run - A good design practice is to pipeline the outputs (i.e., use DFF’s as the output driver)

7. Lecture #26 Page 7 Pipelined Outputs Pipelined Outputs - This gives a smaller Data Uncertainty window on the output - The only consideration is that the output is not present until one clock cycle later

8. Lecture #26 Page 8 Pipelined Outputs Pipelined Outputs - we use a 4 th process for this stage of the State Machine PIPELINED_OUTPUTS : process (CLK) begin if (CLK’event and CLK='1') then Out <= Next_Out; end if; end process;

9. Lecture #26 Page 9 Asynchronous Inputs Asynchronous Inputs - Real world inputs are not phase-locked to the clock - this means an input can change within the Setup/Hold window of the clock - this can send the Machine into an incorrect state - we always want to “synchronize” inputs so that this doesn’t happen

10. Lecture #26 Page 10 Asynchronous Inputs Asynchronous Inputs - We use D-Flip-Flops to take in the input - with one D-Flip-Flop, the input can still occur within the Setup/Hold window - the output of the first DFF may be metastable for a moment of time (t recovery ) - a second DFF is used to latch in the metastable input after it has had time to settle - the output of the second flip-flop is now stable and synchronized as long as: T clk > t recovery + t comb + t setup - where t comb is the delay of any combinational logic in the input path