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ECE543 Intro to Digital Systems Lecture 36 Propagation Delay in Counter Designs II 04/26/2013.

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Presentation on theme: "ECE543 Intro to Digital Systems Lecture 36 Propagation Delay in Counter Designs II 04/26/2013."— Presentation transcript:

1 ECE543 Intro to Digital Systems Lecture 36 Propagation Delay in Counter Designs II 04/26/2013

2 Announcement Postpone homework 9 to 4/29 (Monday) Homework # , 9-1, 9-3, 9-5, 9-8, 9-16 Due May 3 rd (Friday) Final Exam May 13 (Monday), 6-8pm Kingsbury N343 Overview classes May 3 rd and May 6 th ECE543-Intro to Digital Systems 2

3 Outline Overview Propagation delay Timing diagram for counter design Synchronous counter Asynchronous counter Clock period and frequency Computational block design ECE543-Intro to Digital Systems 3

4 ECE543-Intro to Digital Systems 4 Flip-Flop Timing Considerations - Parameters Important timing parameters: Setup and hold times Propagation delay Maximum clocking frequency

5 MOD-16 CLK A B C FF t pd AB AND t pd FF t pd T CLK, min T CLK T CLK >= AND t pd + FF t pd

6 MOD-6 Counter State transition diagram for the MOD-6 counter Circle  state; arrow  state change Clear a MOD-8 counter when a count of six (110) occurs ECE543-Intro to Digital Systems 6

7 MOD-6 Counter B output contains a spike or glitch Caused by the momentary occurrence of the 110 state MOD-6 counter produced by clearing a MOD-8 counter when a count of six (110) occurs. ECE543-Intro to Digital Systems 7

8 CLK A B FF t pd C BC NAND t pd FF t pd ECE543-Intro to Digital Systems

9 CLK A B FF t pd C BC NAND t pd CLR t pd ECE543-Intro to Digital Systems

10 CLK A B FF t pd C BC NAND t pd CLR t pd NAND t pd ECE543-Intro to Digital Systems

11 MOD-6 Counter B output contains a spike or glitch Caused by the momentary occurrence of the 110 state MOD-6 counter produced by clearing a MOD-8 counter when a count of six (110) occurs. ECE543-Intro to Digital Systems 11

12 CLK A B FF t pd C BC ECE543-Intro to Digital Systems T CLK ’

13 ECE543-Intro to Digital Systems 13 Asynchronous (Ripple) Counter Diagram Waveform An asynchronous counter—state is not changed in exact synchronism with the clock. MSBLSB

14 ECE543-Intro to Digital Systems 14 Propagation Delay in Ripple Counters 50ns

15 Homework 7-5 Four-bit ripple counter with frequency f=20MHz (i.e. T=50ns), t pd =20ns= ECE543-Intro to Digital Systems 15 A CLK B C D

16 Homework 7-5 Four-bit ripple counter with frequency f=20MHz (i.e. T=50ns), t pd =20ns. ECE543-Intro to Digital Systems 16 A CLK B C D

17 Propagation Delay Synchronous counter Critical Path = FF t pd + sum of Logic gate t pd s The fastest frequency = 1/ Critical Path Asynchronous (Ripple) counter Critical Path = X * FF t pd (X, # of FFs used) The fastest frequency = 1/ Critical Path ECE543-Intro to Digital Systems 17


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