1. CHAPTER 4 Combinational Logic Design- Arithmetic Operation (Section 4.6&4.9)

2. Overview Binary Addition Binary Addition  Half Adder  Full Adder  Ripple Carry Adder( 并行加法器 )  Carry Look ahead Adder( 超前进位加法器 ) Decimal Addition (Section 4.6.6) Decimal Addition (Section 4.6.6) Binary Comparators (Section 4.7 Binary Comparators (Section 4.7

3. 1-bit Adder Performs the addition of two binary bits. Performs the addition of two binary bits. Four possible operations: Four possible operations:  0+0=0  0+1=1  1+0=1  1+1=10 Circuit implementation requires 2 outputs; one to indicate the sum and another to indicate the carry. Circuit implementation requires 2 outputs; one to indicate the sum and another to indicate the carry.

4. Half Adder Performs 1-bit addition. Performs 1-bit addition. Inputs: A 0, B 0 Inputs: A 0, B 0 Outputs: S 0, C 1 Outputs: S 0, C 1 Index indicates significance, 0 is for LSB and 1 is for the next higher significant bit. Index indicates significance, 0 is for LSB and 1 is for the next higher significant bit. Boolean equations: Boolean equations:  S 0 = A 0 B 0 ’ +A 0 ’ B 0 = A 0  B 0  C 1 = A 0 B 0 1011 0101 0110 0000 C1C1C1C1 S0S0S0S0 B0B0B0B0 A0A0A0A0 Truth Table

5. Half Adder (cont.) S 0 = A 0 B 0 ’ +A 0 ’ B 0 = A 0  B 0 S 0 = A 0 B 0 ’ +A 0 ’ B 0 = A 0  B 0 C 1 = A 0 B 0 C 1 = A 0 B 0 1 bit half adder A0A0A0A0 B0B0B0B0 C1C1C1C1 S0S0S0S0 A0A0A0A0 B0B0B0B0 S0S0S0S0 C1C1C1C1 Logic DiagramBlock Diagram

6. n-bit Addition Design an n-bit binary adder which performs the addition of two n-bit binary numbers and generates a n-bit sum and a carry out. Design an n-bit binary adder which performs the addition of two n-bit binary numbers and generates a n-bit sum and a carry out. Example: Let n=4 C out C 3 C 2 C 1 C 0 1 1 0 1 0 A 3 A 2 A 1 A 0 1 1 0 1 + B 3 B 2 B 1 B 0 +1 1 0 1 --------------------- ---------- S 3 S 2 S 1 S 0 1 0 1 0 Example: Let n=4 C out C 3 C 2 C 1 C 0 1 1 0 1 0 A 3 A 2 A 1 A 0 1 1 0 1 + B 3 B 2 B 1 B 0 +1 1 0 1 --------------------- ---------- S 3 S 2 S 1 S 0 1 0 1 0

7. Full Adder Full adder (for higher-order bit addition) Full adder (for higher-order bit addition) Combinational circuit that performs the additions of 3 bits (two bits and a carry-in bit) Combinational circuit that performs the additions of 3 bits (two bits and a carry-in bit) 1 bit full adder AiAiAiAi BiBiBiBi C i+1 SiSiSiSi CiCiCiCi

8. Full Adder (cont.) 10110 01001 10101 10011 11111 0 1 0 CiCiCiCi 0110 0100 0000 C i+1 SiSiSiSi BiBiBiBi AiAiAiAi The K-maps for The K-maps for  C i+1 :  S i : 1110 0100 BiCiBiCiBiCiBiCi AiAiAiAi 0101 1010 BiCiBiCiBiCiBiCi AiAiAiAi

9. Full Adder (cont.) Boolean equations: Boolean equations:  C i+1 = A i B i + A i C i + B i C i  S i = A i B i ’ C i ’ + A i ’B i ’C i + A i ’B i C i ’ + A i B i C i = A i  B i  C i You can design full adder circuit directly from the above equations (requires 3 ANDs and 1 OR for C i+1 and 2 XORs for S i ) You can design full adder circuit directly from the above equations (requires 3 ANDs and 1 OR for C i+1 and 2 XORs for S i )

10. Full Adder using 2 Half Adders A full adder can also be realized with two half adders and an OR gate, since C i+1 can also be expressed as: A full adder can also be realized with two half adders and an OR gate, since C i+1 can also be expressed as: C i+1 = A i B i + A i B i ’ C i + A i ’ B i C i C i+1 = A i B i + A i B i ’ C i + A i ’ B i C i = A i B i + (A i B i ’ + A i ’ B i )C i = A i B i + (A i  B i )C i and S i = A i  B i  C i and S i = A i  B i  C i AiAiAiAi BiBiBiBi CiCiCiCi C i+1 SiSiSiSi

11. n-bit Combinational Adders Perform parallel multi-bit addition Perform parallel multi-bit addition Ripple Carry Adder ( 并行加法器 ) Ripple Carry Adder ( 并行加法器 )  Simple design  Time consuming. Why? (you ’ ll see in a bit!) Carry Look ahead Adder ( 超前进位加法器 ) Carry Look ahead Adder ( 超前进位加法器 )  More complex than ripple-carry adder  Reduces circuit delay

12. n-bit Ripple Carry Adder Constructed using n 1-bit full adder blocks in parallel. Constructed using n 1-bit full adder blocks in parallel. Cascade the full adders so that the carry out from one becomes the carry in to the next higher bit position. Cascade the full adders so that the carry out from one becomes the carry in to the next higher bit position.

13. Example: 4-bit Ripple Carry Adder C 4 C3 C2 C1 C0 A3 A2 A1 A0 +B3 B2 B1 B0 -------------- S3 S2 S1 S0 C 4 C3 C2 C1 C0 A3 A2 A1 A0 +B3 B2 B1 B0 -------------- S3 S2 S1 S0

14. Ripple Carry Adder Delay Circuit delay in an n-bit ripple carry adder is determined by the delay on the carry path from the LSB (C 0 ) to the MSB (C n ). Circuit delay in an n-bit ripple carry adder is determined by the delay on the carry path from the LSB (C 0 ) to the MSB (C n ). Let the delay in a 1-bit FA be Δ. Then, the delay of an n-bit ripple carry adder is nΔ. Let the delay in a 1-bit FA be Δ. Then, the delay of an n-bit ripple carry adder is nΔ.

15. Carry Look ahead Adder Alternative design for a combinational n-bit adder. Alternative design for a combinational n-bit adder. Practical design with reduced delay at the expense of more complex hardware. Practical design with reduced delay at the expense of more complex hardware. Derived from a transformation of the ripple carry adder design. Derived from a transformation of the ripple carry adder design.

16. Carry Lookahead Adder Design From a FA, separate between carry generation (a new carry signal is generated, i.e. C out =1) and carry propagation (an existing C in is propagated to C out ) From a FA, separate between carry generation (a new carry signal is generated, i.e. C out =1) and carry propagation (an existing C in is propagated to C out ) Generate: G i = A i B i : if 1, C i+1 =1 Generate: G i = A i B i : if 1, C i+1 =1 Propagate: P i = A i  B i : if 1, C i+1 = C i Propagate: P i = A i  B i : if 1, C i+1 = C i Partial Full Adder (PFA)Full Adder (FA) BiBiBiBi BiBiBiBi AiAiAiAi CiCiCiCi CiCiCiCi C i+1 SiSiSiSi SiSiSiSi GiGiGiGi PiPiPiPi AiAiAiAi

17. Carry Lookahead Adder Design (cont.) C i+1 = G i + P i C i C i+1 = G i + P i C i PFA design breaks S functionality apart from G/P functionality PFA design breaks S functionality apart from G/P functionality

18. Carry Look ahead Adder (cont.) Does this (design in previous slide) solve the long delay problem? Does this (design in previous slide) solve the long delay problem? No, carry out still “ ripples ” ! No, carry out still “ ripples ” ! Idea: use two levels of logic to generate carry out of any block C i in terms of carry in C 0 and addend bits A i and B i Idea: use two levels of logic to generate carry out of any block C i in terms of carry in C 0 and addend bits A i and B i

19. Block CLA Implement: Implement:  C 1 = G 0 +P 0 C 0  C 2 = G 1 +P 1 C 1 = G 1 +P 1 (G 0 +P 0 C 0 ) = G 1 +P 1 G 0 +P 1 P 0 C 0  C 3 = G 2 + P 2 C 2 = G 2 +P 2 G 1 +P 2 P 1 G 0 +P 2 P 1 P 0 C 0  C 4 = G 3 +P 3 G 2 +P 3 P 2 G 1 +P 3 P 2 P 1 G 0 + P 3 P 2 P 1 P 0 C 0 = G 0-3 + P 0-3 C 0 Group carry generate Group carry propagate

20. Generate/Propagate logic of a 4-bit CLA -- C 0 … C n-1 have a 2-gates delay G 0-3 +P 0-3 C 0 -- C 4 = G 0-3 +P 0-3 C 0 has a 3-gates delay

21. 4.6.4 Using MSI Adders as Subtractors MSI Adders MSI Adders  74LS83 : 4Bits carry look ahead adder device  Cascading four 74LS83 four-bit adders to form 1 16bit adder (Fig. 4.55) Subtractor(P155) Subtractor(P155)  Using 2s complement to realize subtraction

22. 4.6.5 Using an MSI Adders as BCD to Excess-3 code converter  Page 156

23. 4.6.6 BCD Adder BCD Decimal Adder: BCD Decimal Adder:  Requires 8 inputs (4 bits per decimal number)  5 outputs indicate the decimal sum and the carry  Remember BCD addition rules: Add 0110 to the sum if it is greater than 1010 to correct the carry bit (P157)

24. Binary Coded Decimal (BCD) Adder Addend 4-bit binary adder z3 z2 z1 z0 4-bit binary adder S3 S2 S1 S0 BCD sum 0 K C C = K + z3z2 + z3z1

25. 4.7 Binary Comparators Single bit comparator Single bit comparator A EQ B = A ’ B ’ + AB A > B = AB ’ A< B = A ’ B(P159, Fig 4.62) Two-bit comparator Two-bit comparator Iterative Design of multiple-bit comparators Iterative Design of multiple-bit comparators  Basic iterative circuit model (Fig 4.64)  Truth table for a single cell of a binary comparator (Table 4.19)

26. 4.8 Arithmetic Logic Unit (ALU) Combining all possible combinational logic functions (Addition, Subtraction, AND, OR, etc.) into a single IC. Combining all possible combinational logic functions (Addition, Subtraction, AND, OR, etc.) into a single IC. Select bits are used to select one of the functions to be implemented (See Table 4.21, P164) Select bits are used to select one of the functions to be implemented (See Table 4.21, P164)

27. Array Multipliers (Omitted) Array Multipliers (Omitted) Tri-state buffers (P170) Tri-state buffers (P170) 4.11 Combinational Logic Hazards (P171) 4.11 Combinational Logic Hazards (P171)  Static ‘ 1 ’ hazard  Static ‘ 0 ’ hazard  Ex. P = xy ’ + yz