# Kuliah Rangkaian Digital Kuliah 7: Unit Aritmatika

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Kuliah Rangkaian Digital Kuliah 7: Unit Aritmatika

Topic #7 – Arithmetic Units

(Equality) Comparators (using XOR)
1-bit comparator 4-bit comparator

Half adder Adds two 1-bit input to produce a sum and a carry-out
Does not account for carry-in S = X’·Y + X·Y = XY Cout = X·Y Inputs Outputs Y 1 S X Cout X Y S Cout

Full adder Building block to realize binary arithmetic operations
1-bit-wide adder with carry-in, produces sum and carry-out Truth table: X Y Cin S Cout

Designing full adder 1 00 01 11 10 Cout S 1 00 01 11 10
Cin X 1 Y XY 2 3 6 7 4 5 Cout S Cin X 1 Y XY 2 3 6 7 4 5 S = X’·Y’·(Cin) + X·Y’·(Cin)’ + X·Y’·(Cin)’ + X·Y·(Cin) = X Å Y Å (Cin) Cout = XY + X(Cin) + Y(Cin)

Resulting circuit

X’Y’C-in XY’C-in’ Sum S X’YC-in’ XYC-in X’ X Y’ Y C-in C-in’ X X’ Y Y’ C-in C-in’ Full Adder X Y S C-in C-out XY YC-in C-out XC-in X Y C-in

Q: Do we need C4 for a 4-bit 2’s complement addition?
Ripple adder Speed limited by carry chain 2 per full adder  2n for an n-bit adder Approach: eliminate or reduce carry chain Carry look-ahead: compute Cin directly from external inputs Q: Do we need C4 for a 4-bit 2’s complement addition?

Let Ci+1 = (Xi·Yi)+ (Xi+Yi)· Ci = Gi + Pi · Ci For a 4-bit adder … C1 = G0 + P0·C0 C2 = G1 + P1·C1 = G1 + P1·G0 + P1·P0·C0 C3 = G2 + P2·G1 + P2·P1·G0 + P2·P1·P0·C0 C4 = G3 + P3·G2 + P3·P2·G1 + P3·P2·P1·G0 + P3·P2·P1·P0·C0 where Gi = Xi · Yi Pi = Xi + Yi This is a 3 level circuit including generating the Gs and Ps Rule of thumb: one carry look-ahead circuit every 4-bit

Gs and Ps are also useful for generating the sums

Subtraction Recall our discussion on subtraction for 2’s complement … X – Y = X + Y + 1 Invert all bits of Y and set Cin to 1 Example: 4-bit subtractor using 4-bit adder Add a control circuit in ALU s.t. same circuit can be used for both addition and subtraction 4-bit Adder X3 X2 X1 X0 D3 D2 D1 D0 C-in C-out C4 Y3 Y2 Y1 Y0 C0 = 1 S3 S2 S1 S0

Multipliers 8x8 multiplier

Faster carry chain

Binary Multiplication
An n-bit X n-bit multiplier can be realized in combinational circuitry by using an array of n-1 n-bit adders where is adder is shifted by one position. For each adder one input is the multiplied by 0 or 1 (using AND gates) depending on the multiplier bit, the other input is n partial product bits. X3 X2 X1 X0 x Y3 Y2 Y1 Y0 __________________________ X3.Y0 X2.Y0 X1.Y0 X0.Y0 X3.Y1 X2.Y1 X1.Y1 X0.Y1 X3.Y2 X2.Y2 X1.Y2 X0.Y2 X3.Y3 X2.Y3 X1.Y3 X0.Y3 _______________________________________________________________________________________________________________________________________________ P P P P P P P P0

4x4 Array Multiplier