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Kuliah Rangkaian Digital Kuliah 7: Unit Aritmatika Teknik Komputer Universitas Gunadarma.

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Presentation on theme: "Kuliah Rangkaian Digital Kuliah 7: Unit Aritmatika Teknik Komputer Universitas Gunadarma."— Presentation transcript:

1 Kuliah Rangkaian Digital Kuliah 7: Unit Aritmatika Teknik Komputer Universitas Gunadarma

2 Topic #7 – Arithmetic Units ComparatorAdders Half-adder & Full-adder Half-adder & Full-adder Carry-ripple adder & carry-look-ahead adder Carry-ripple adder & carry-look-ahead adder Overflow detection Overflow detectionSubtractorMultiplier

3 (Equality) Comparators (using XOR) 1-bit comparator 4-bit comparator

4 Adds two 1-bit input to produce a sum and a carry-out Does not account for carry-in Does not account for carry-in XYXY S C out Half adder S = X’·Y + X·Y = X  Y C out = X·Y Inputs Outputs Y0101Y0101 S0110S0110 X0011X0011 C out 0 1

5 Full adder Building block to realize binary arithmetic operations 1-bit-wide adder with carry-in, produces sum and carry- out Truth table: XYC in SC out

6 S Cin X Y Cin XY Cin X Y Cin XY Cout S = X’·Y’·(Cin) + X·Y’·(Cin)’ + X·Y’·(Cin)’ + X·Y·(Cin) = X  Y  (Cin) Cout = XY + X(Cin) + Y(Cin) Designing full adder

7 Resulting circuit

8 XY YC-in C-out XC-in X X Y C-in Y YY’ Y XX’ X C-in C-in’ C-in X’Y’C-in XY’C-in’ Sum S X’YC-in’ XYC-in X’ X X Y’ Y Y C-in Y C-in’ Full Adder XY S C-in C-out Alternative: full adder using AND-OR

9 Ripple adder Speed limited by carry chain 2  per full adder  2n  for an n-bit adder 2  per full adder  2n  for an n-bit adder Approach: eliminate or reduce carry chain Carry look-ahead: compute Cin directly from external inputs Carry look-ahead: compute Cin directly from external inputs Q: Do we need C4 for a 4-bit 2’s complement addition?

10 Let C i+1 = (X i ·Y i )+ (X i +Y i )· C i = G i + P i · C i For a 4-bit adder … C 1 = G 0 + P 0 ·C 0 C 2 = G 1 + P 1 ·C 1 = G 1 + P 1 ·G 0 + P 1 ·P 0 ·C 0 C 3 = G 2 + P 2 ·G 1 + P 2 ·P 1 ·G 0 + P 2 ·P 1 ·P 0 ·C 0 C 4 = G 3 + P 3 ·G 2 + P 3 ·P 2 ·G 1 + P 3 ·P 2 ·P 1 ·G 0 + P 3 ·P 2 ·P 1 ·P 0 ·C 0 where G i = X i · Y i P i = X i + Y i where G i = X i · Y i P i = X i + Y i This is a 3 level circuit including generating the Gs and Ps Rule of thumb: one carry look-ahead circuit every 4-bit Rule of thumb: one carry look-ahead circuit every 4-bit Carry look-ahead adder

11 Carry look-ahead circuit Gs and Ps are also useful for generating the sums

12 16-bit carry ripple adder

13 16-bit carry look-ahead adder

14 Subtraction Recall our discussion on subtraction for 2’s complement … X – Y = X + Y + 1 X – Y = X + Y + 1 Invert all bits of Y and set C in to 1 Invert all bits of Y and set C in to 1 Example: 4-bit subtractor using 4-bit adder Add a control circuit in ALU s.t. same circuit can be used for both addition and subtraction 4-bit Adder X3 X2 X1 X0 D3 D2 D1 D0 C-in C-out C4 Y3 Y2 Y1 Y0 C0 = 1 S3 S2 S1 S0

15 Multipliers 8x8 multiplier

16 Full-adder array

17 Faster carry chain

18 Binary Multiplication An n-bit X n-bit multiplier can be realized in combinational circuitry by using an array of n-1 n- bit adders where is adder is shifted by one position. For each adder one input is the multiplied by 0 or 1 (using AND gates) depending on the multiplier bit, the other input is n partial product bits. X3 X2 X1 X0 x Y3 Y2 Y1 Y0 __________________________ X3.Y0 X2.Y0 X1.Y0 X0.Y0 X3.Y1 X2.Y1 X1.Y1 X0.Y1 X3.Y2 X2.Y2 X1.Y2 X0.Y2 X3.Y3 X2.Y3 X1.Y3 X0.Y3 _______________________________________________________________________________________________________________________________________________ P7 P6 P5 P4 P3 P2 P1 P0

19 4x4 Array Multiplier


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