1. EE3A1 Computer Hardware and Digital Design Lecture 5 Testbenches and Memories in VHDL

2. Introduction  Testbenches u VHDL description of environment u Apply test inputs u Look at outputs  More advanced ways to represent data  Memories u Needed for the assignment

3. Testbenches  Would like to describe test inputs in VHDL u Powerful u Portable

4. A simulation example from the lab LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY nandgate IS PORT ( a, b: IN STD_LOGIC; c: OUT STD_LOGIC ); END ENTITY nandgate; ARCHITECTURE simple OF nandgate IS BEGIN c <= a NAND b; END ARCHITECTURE simple;

5. A simulation example from the lab  Used stimulators in ActiveHDL u Not portable to other VHDL products u Not very powerful  We’d like to describe test inputs in VHDL

6. A simulation example from the lab  We need to know VHDL way to: u represent behaviour of a and b u Low then high then low again u apply these inputs to the gate

7. Multiple assignment to signals in1 <= ‘0’, ‘1’ AFTER 20 NS, ‘0’ AFTER 60 NS; in2 <= ‘0’, ‘1’ AFTER 40 NS, ‘0’ AFTER 80 NS;  Normal VHDL assignment runs when RHS signal changes  There are no signals on RHS, only literal values  Statements run exactly once at beginning of simulation  This type of assignment is exempt from inertial behaviour  Multiple transitions can co-exist on queue

8. Result on event queue Signal namein1In2 Present valueUU Future value0 1 0 Transition time  20 60  40 80 in1 <= ‘0’, ‘1’ AFTER 20 NS, ‘0’ AFTER 60 NS; in2 <= ‘0’, ‘1’ AFTER 40 NS, ‘0’ AFTER 80 NS;

9. A test bench for the NAND gate  Test bench represents “world around the device we’re simulating”  Contains VHDL simulation of u input generator (signal generator) u output observer (logic analyzer)

10. A test bench for the NAND gate  It’s a closed system with no inputs or outputs: LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY mytestbench IS END ENTITY mytestbench;

11. A test bench for the NAND gate  It contains internal signals: u in1, in2 that model a signal generator unit u out1 that models the logic analyzer unit ARCHITECTURE test OF mytestbench IS SIGNAL in1, in2, out1: STD_LOGIC; BEGIN

12. A test bench for the NAND gate  It contains one copy of the device we want to test u in1, in2 are connected to its inputs u out1 is connected to its outputs G1: ENTITY work.nandgate(simple) PORT MAP (a=>in1, b=>in2, c=>out1);

13. A test bench for the NAND gate  We need to say how in1 and in2 change with time in1 <= ‘0’, ‘1’ AFTER 20 NS, ‘0’ AFTER 60 NS; in2 <= ‘0’, ‘1’ AFTER 40 NS, ‘0’ AFTER 80 NS;

14. A test bench for the NAND gate ARCHITECTURE test OF mytestbench IS SIGNAL in1, in2, out1: STD_LOGIC; BEGIN G1: ENTITY work.nandgate(simple) PORT MAP (a=>in1, b=>in2, c=>out1); in1 <= ‘0’, ‘1’ AFTER 20 NS, ‘0’ AFTER 60 NS; in2 <= ‘0’, ‘1’ AFTER 40 NS, ‘0’ AFTER 80 NS; END ARCHITECTURE test;

15. More powerful features for data  We can use a variety of types: ARCHITECTURE simple OF example IS SIGNAL a: CHARACTER; SIGNAL b: INTEGER; SIGNAL c: STD_LOGIC; BEGIN END ARCHITECTURE simple;

16. More powerful features for data  We can initialize during declaration: ARCHITECTURE init OF example IS SIGNAL a: CHARACTER :='H'; SIGNAL b: INTEGER :=5; SIGNAL c: STD_LOGIC :='X'; BEGIN END ARCHITECTURE init;

17. Arrays  An array is u list of items u all of same type u indexed by a number.

18. ARCHITECTURE simple OF example2 IS TYPE list11 IS ARRAY (0 TO 10) OF CHARACTER; SIGNAL a: LIST11 := ('H','e','l','l','o',' ','t','h','e','r','e'); SIGNAL b: LIST11 := ('H','o','w',' ','a','r','e',' ','y','o','u'); BEGIN END ARCHITECTURE simple; Arrays  Define type list11  Use this type to define arrays a and b u a(0) has the value ’H’, u a(1) is ‘e’, u a(10) is ‘e’ 0 1 2 3 4 5 6 7 8 9 10

19. Features of arrays ARCHITECTURE example OF aggregate IS SIGNAL nibble1, nibble2: STD_LOGIC_VECTOR ( 0 TO 3 ); BEGIN nibble1 <= ( '0','1','0','0'); nibble2 <= ( '0','0','1','0'); END ARCHITECTURE example;  Positional assignment nibble1 <= ( '0','1','0','0'); 0 1 2 3

20. Features of arrays ARCHITECTURE example OF aggregate IS SIGNAL nibble1, nibble2: STD_LOGIC_VECTOR ( 0 TO 3 ); BEGIN nibble1 <= ( '0','1','0','0'); nibble2 <= ( '0','0','1','0'); END ARCHITECTURE example;  Named assignment nibble1 '1', 0 => '0', 3 => '0', 2 => '0');  Another way is to write this nibble1 '1', OTHERS => '0'); 0 1 2 3

21. Features of arrays  Useful trick nibble1 '1');  Sets all of the elements of nibble1 to '1'.

22. Concatenation: the & operator  merges two vectors to produce a longer vector. ARCHITECTURE example OF aggregate IS SIGNAL byte: STD_LOGIC_VECTOR ( 0 TO 7 ); SIGNAL nibble1, nibble2: STD_LOGIC_VECTOR ( 0 TO 3 ); BEGIN nibble1 <= ( '0','1','0','0'); nibble2 <= ( '0','0','1','0'); byte <= nibble1 & nibble2; END ARCHITECTURE example;  byte gets value ( '0','1','0','0','0','0','1','0')

23. Concatenation: the & operator  merges two vectors to produce a longer vector. ARCHITECTURE example OF aggregate IS SIGNAL byte: STD_LOGIC_VECTOR ( 0 TO 7 ); SIGNAL nibble1, nibble2: STD_LOGIC_VECTOR ( 0 TO 3 ); BEGIN nibble1 <= ( '0','1','0','0'); nibble2 <= ( '0','0','1','0'); byte <= nibble1 & nibble2; END ARCHITECTURE example;  byte gets value ( '0','1','0','0','0','0','1','0')

24. Literals: “string” Array of ‘char’  String is an array of characters  These are equivalent: nibble1 <= ( '0','1','0','0'); nibble1 <= "0100";

25.  All equivalent: a <= "010011001010"; a <= B"010011001010"; --binary a <= O"2312"; --octal a <= X"4CA” --hexadecimal Literals: Number base  Octal conversion: u convert groups of 3 bits to corresponding octal digit

26. Literals: Number base  All equivalent: a <= "010011001010"; a <= B"010011001010"; --binary a <= O"2312"; --octal a <= X"4CA” --hexadecimal  Hexadecimal conversion: u convert groups of 4 bits to corresponding hex digit

27.  All equivalent: a <= "010011001010"; a <= B"010011001010"; --binary a <= O"2312"; --octal a <= X"4CA” --hexadecimal Literals: Number base  More readable: a <= B"0100_1100_1010";  but not a <= "0100_1100_1010"; -- Wrong! Needs B

28. Type conversion  VHDL is strongly typed language. ARCHITECTURE wrong OF example3 IS SIGNAL a: INTEGER; SIGNAL b: STD_LOGIC_VECTOR(7 DOWNTO 0) := X“FF”; BEGIN a <= b; --WRONG. This will not compile !! END ARCHITECTURE wrong;  FF = 1111 1111  Need type conversion  Otherwise we don’t know if 11111111 is –1 or 255 Type mismatch in assignment

29. Type conversion  A strongly typed language needs explicit type conversion USE IEEE.STD_LOGIC_UNSIGNED.ALL; ARCHITECTURE correct OF example3 IS SIGNAL a: INTEGER; SIGNAL b: STD_LOGIC_VECTOR(7 DOWNTO 0) := X“FF”; BEGIN a <= CONV_INTEGER(b); END ARCHITECTURE correct; FF represents 255  This is unambiguous  It works OK

30. Questions  Which of the following is not equivalent a) my_signal <= “101000111010”; b) my_signal <= B”1010_0011_1010”; c) my_signal <= X”B3B”; d) my_signal <= O”5072”; e) my_signal <= B”101_000_1110_10”;

31. Questions  Which of the following is not equivalent a) my_signal <= “101000110000”; b) my_signal <= B”1010_0011_0000”; c) my_signal <= X”A30”; d) my_signal <= O”2060”; e) my_signal <= B”101_000_1100_00”;

32. Questions  my_signal is std_logic_vector(7 downto 0)  What value does my_signal get as a result of  my_signal ’1’,others=>’0’); a) “00000010” b) “01000000” c) “10000000” d) “00000001” e) None of the above

33. The ALU example LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.std_logic_signed.ALL; ENTITY alu IS PORT ( a, b: IN STD_LOGIC_VECTOR(15 DOWNTO 0); opcode: IN STD_LOGIC_VECTOR(1 DOWNTO 0); c: OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END ENTITY alu;

34. The ALU example ARCHITECTURE simple OF alu IS BEGIN c <= a + b WHEN opcode=”00” ELSE a - b WHEN opcode=”01” ELSE a OR b WHEN opcode=”10” ELSE a AND b WHEN opcode=”11”; END ARCHITECTURE simple;

35. Test bench for the ALU LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY mytestbench IS END ENTITY mytestbench; Create closed system (no inputs or outputs)

36. Test bench for the ALU LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY mytestbench IS END ENTITY mytestbench; ARCHITECTURE test OF mytestbench IS SIGNAL in1, in2, out1: STD_LOGIC_VECTOR (15 DOWNTO 0); SIGNAL in3: STD_LOGIC_VECTOR (1 DOWNTO 0); BEGIN Create closed system (no inputs or outputs) Internally it has signals in1, in2 in3 that will attach to ALU inputs and out1 will attach to ALU output

37. Test bench for the ALU G1: ENTITY work.alu(simple) PORT MAP (a=>in1, b=>in2, opcode=>in3, c=>out1); in1 <= X”0001”, X”0FAF” AFTER 20 NS, X”F000” AFTER 40 NS; in2 <= X”0100”, X”7FFF” AFTER 10 NS, X”FFFF” AFTER 30 NS; in3 <= “00”; END ARCHITECTURE test; Create one instance of the ALU and wire it up Define how signal values should change with time

38. Memories  Read-only memory (ROM): u Holds list of items u One item selected by input address

39. Memory example: exam marks StudentMark 072 149 267 353 443 557 661 737 848 955 1079 1151 1240 1361 1458 1562 StudentMark 048 131 243 335 42B 539 63D 725 830 937 A4F B33 C28 D3D E3A F3E In Hex

40. Memory example: exam marks In ROM StudentMark 048 131 243 335 42B 539 63D 725 830 937 A4F B33 C28 D3D E3A F3E Input Student-ID (4-bit, or 1 hex digit) Output student mark (8-bit or 2 hex digits)

41. Memory example: exam marks In ROM StudentMark 048 131 243 335 42B 539 63D 725 830 937 A4F B33 C28 D3D E3A F3E Input Student-ID (4-bit, or 1 hex digit) Output student mark (8-bit or 2 hex digits) 6 3D

42. ENTITY for ROM Example LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; USE IEEE.std_logic_unsigned.ALL; ENTITY rom IS PORT ( address: IN STD_LOGIC_VECTOR(3 DOWNTO 0); data : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END ENTITY rom;

43. Setting up ROM data TYPE rom_array IS ARRAY ( 0 TO 15 ) OF STD_LOGIC_VECTOR ( 7 DOWNTO 0 ); SIGNAL rom_data: rom_array := ( X"48", X"31", X"43", X"35", X"2B", X"39", X"3D", X"25", X"30", X"37", X"4F", X"33", X"28", X"3D", X"3A", X"3E");

44. Reading out selected data item data <= rom_data ( CONV_INTEGER (address) );

45. ARCHITECTURE of the ROM ARCHITECTURE simple OF rom IS TYPE rom_array IS ARRAY ( 0 TO 15 ) OF STD_LOGIC_VECTOR ( 7 DOWNTO 0 ); SIGNAL rom_data: rom_array := ( X"48", X"31", X"43", X"35", X"2B", X"39", X"3D", X"25", X"30", X"37", X"4F", X"33", X"28", X"3D", X"3A", X"3E"); BEGIN data <= rom_data ( CONV_INTEGER (address) ); END ARCHITECTURE simple;

46. Test bench for the ROM LIBRARY IEEE; USE IEEE.std_logic_1164.ALL; ENTITY rom_test IS END ENTITY rom_test; ARCHITECTURE simple OF rom_test IS SIGNAL input_address: STD_LOGIC_VECTOR (3 DOWNTO 0); SIGNAL output_data: STD_LOGIC_VECTOR (7 DOWNTO 0); Create closed system (no inputs or outputs) Internally it has signals that attach to input and output of device being tested

47. BEGIN g1: ENTITY work.rom(simple) PORT MAP ( address=>input_address, data=>output_data); input_address <= X"0", X"1" AFTER 20 NS, X"2" AFTER 40 NS, X"3" AFTER 60 NS; END ARCHITECTURE simple; Test bench for the ROM

48. StudentMark 048 131 243 335 42B 539 63D 725 830 937 A4F B33 C28 D3D E3A F3E  As address is given,  Indexed data item appears at output

49. Summary  Building blocks for assignment u Test benches u ALU u Memory u Advanced features of data definition