1. Lab Lecture 3 VHDL Architecture styles and Test Bench -Aahlad

2. Architecture Styles Structural Style of Modeling (to represent interconnected components) Concurrent Style of Modeling ( to represent data flow) Sequential Style of Modeling ( to represent behavior ) Any combination of the above three

3. Architecture Body Architecture body has two parts, namely declaration and instantiation. architecture ABC of entity DEF is component…… signal…… begin work to be done, process…. end ABC; Declaration of signals, components…. Instantiation

4. Structural Modeling-Brief Overview Component : An entity X, when used in another entity Y, becomes a component for that entity Y. So a component is also an entity depending on the level at which it is modelled.

5. Structural Modeling-Brief Overview architecture HA_STRUCTURE of HALF_ADDER is component XOR2 port (X, Y: in BIT; Z: out BIT); end component; component AND2 port (L, M: in BIT; N: out BIT); end component; begin X1: XOR2 port map (A, B, SUM); A1: AND2 port map (A, B, CARRY); end HA_STRUCTURE; Component Declaration Component Instantiation

6. Structural Modeling-Brief Overview The components declared in the architecture body ( i.e. XOR2 and AND2 in the previous example ) must be either defined in the library or a separate entity having a behavioral description of the component. Components must be instantiated with labels (i.e. X1 and A1) and port mapped to the signals of the current architecture.

7. architecture DEC_STR of DECODER2x4 is component INV port (A: in BIT; Z: out BIT); end component; component NAND3 port (A, B, C: in BIT; Z: out BIT); end component; begin I0: INV port map (A, ABAR); I1: INV port map (B, BBAR); N0: NAND3 port map (ABAR, BBAR, ENABLE, Z(0)); N1: NAND3 port map (ABAR, B, ENABLE, Z(1)); N2: NAND3 port map (A, BBAR, ENABLE, Z(2)); N3: NAND3 port map (A, B, ENABLE, Z(3)); end DEC_STR; Will this code compile without errors? Assume all the inputs and outputs are declared in the entity

8. Structural Modeling-Brief Overview We missed the intermediate signals ABAR and BBAR in the previous programs. Signal declarations represent wires that interconnect various components of a digital system. As in real physical systems signals initialization doesn’t happen instantaneously. There is always a delay associated with it.

9. architecture DEC_STR of DECODER2x4 is component INV port (A: in BIT; Z: out BIT); end component; component NAND3 port (A, B, C: in BIT; Z: out BIT); end component; signal ABAR, BBAR: BIT;---signal declaration before begin begin I0: INV port map (A, ABAR); I1: INV port map (B, BBAR); N0: NAND3 port map (ABAR, BBAR, ENABLE, Z(0)); N1: NAND3 port map (ABAR, B, ENABLE, Z(1)); N2: NAND3 port map (A, BBAR, ENABLE, Z(2)); N3: NAND3 port map (A, B, ENABLE, Z(3)); end DEC_STR;

10. Data Flow Modeling-Brief Overview The flow of data through the entity is expressed primarily using concurrent signal assignment statements. A concurrent signal assignment statement is executed only when a signal used in the expression on the right hand side has a event on it. In data flow model order of statements is not important because all the statements are executed in parallel.

11. Concurrent Statements All statements other than statements within the process in the architecture instantiation part (after begin) are concurrent statements. Process statements are concurrent statements. Confused??

12. architecture HA_CONCURRENTof HALF_ADDER is begin SUM <= A xor B; CARRY <= A and B ; end HA_CONCURRENT

13. Data Flow Modeling-Brief Overview In the previous example whenever there is an event on A or B both SUM and CARRY will be executed in parallel. The order of SUM and CARRY in the architecture both is of no importance as they both are executed in parallel.

14. architecture dec_dataflgw of DECODER2x4 is signal ABAR, BBAR: BIT; begin Z(3) <= not (A and B and ENABLE); - statement 1 Z(0) <= not (ABAR and BBAR and ENABLE); - statement 2 BBAR <= not B; - statement 3 Z(2) <= not (A and BBAR and ENABLE); - statement 4 ABAR <= not A; - statement 5 Z(1 ) <= not (ABAR and B and ENABLE); - statement 6 end DEC_DATAFLOW; For an event on B at a time T statements 1, 3, 6 are executed at T and new values are assigned to signals Z(3), BBAR, Z(1) at T+Δ. Statements 2 and 4 are executed at time T+ Δ and the new values are assigned to Z(0) and Z(2) at T+2 Δ time interval.

15. Mixed Modeling-Identify the modeling styles architecture FA_MIXED of FULL_ADDER is component XOR2 port (A, B: in BIT; Z: out BIT); end component; signal S1: BIT; begin X1: XOR2 port map (A, B, S1 ); process (A, B, CIN) variable T1, T2, T3: BIT; begin T1 :=A and B; T2 := B and CIN; T3:=A and CIN; COUT <= T1 or T2 or T3; end process; SUM <= S1 xor CIN; end FA_M!XED;

16. Components A component can be instantiated any number of times. However, each instantiation should have a unique label. Component declaration component component-name port ( list-of-interface-ports ) ; end component ;

17. Components The component name must either be an entity in the library or must be explicitly bound to an entity. Component declaration appears in the declaration part of the architecture body i.e. before begin.

18. Components Component instantiation statement defines subcomponent of the entity in which it appears. It associates the signals in the entity with the ports of the subcomponent. component-label: component-name port map ( association-list); Signal association can be performed either by Position association or Named association.

19. entity HALF_ADDER is port (A, B: in BIT; SUM, CARRY: out BIT); end HALF_ADDER architecture HA_STRUCTURE of HALF_ADDER is component XOR2 port (X, Y: in BIT; Z: out BIT); end component; component AND2 port (L, M: in BIT; N: out BIT); end component; begin X1: XOR2 port map (A, B, SUM); A1: AND2 port map (A, B, CARRY); end HA_STRUCTURE

20. Position Association Example -- Component declaration: component NAND2 port (A, B: in BIT; Z: out BIT); end component; signal S1, S2, S3, X, Y, Z1 : std_logic; begin -- Component instantiation: N1: NAND2 port map (S1, S2, S3); N2: NAND2 port map (Z1, Y, X); S1  A, S2  B, S3  Z Z1  A, Y  Z, X  B ---Find the mistake?

21. Named Association -- Component declaration: component NAND2 port (A, B: in BIT; Z: out BIT); end component; signal S1, S2, S2 : std_logic; begin -- Component instantiation: N1: NAND2 port map (A=>S1, B=>S2, Z=>S3);

22. Example of multiple instantiation architecture PARITY_STR of PARITY_9_BIT is component XOR2 port (A, B: in BIT; Z: out BIT); end component; component INV2 port (A: in BIT; Z: out BIT); end component; signal E0, E1, E2, E3, F0, F1, H0: BIT; begin XE0: XOR2 port map (D(0), D(1), E0); XE1: XOR2 port map (D(2), D(3), E1); XE2: XOR2 port map (D(4), D(5), E2); XE3: XOR2 port map (D(6), D(7), E3); XF0: XOR2 port map (E0, E1, F0); XF1: XOR2 port map (E2, E3, F1); XH0: XOR2 port map (F0, F1, H0); XODD: XOR2 port map (H0, D(8), ODD); XEVEN: INV2 port map (ODD, EVEN); end PARITY_STR;

23. Test Bench A Test bench always has an empty entity. Test bench is used for simulation and to check the behavior of the code. Test bench uses component instantiation to supply the inputs. Lets look at an example from lab 2.

24. LIBRARY IEEE; USE IEEE.std_logic_1164.all; USE IEEE.std_logic_arith.all; USE IEEE.std_logic_unsigned.all; USE IEEE.STD_LOGIC_TEXTIO.ALL; USE STD.TEXTIO.ALL; ENTITY testbench IS END testbench; Empty Entity

25. ARCHITECTURE testbench_arch OF testbench IS COMPONENT tut1 PORT ( A : in std_logic; B : in std_logic; C : in std_logic; D : in std_logic; Y : out std_logic ); END COMPONENT; SIGNAL X_A : std_logic := '0'; SIGNAL X_B : std_logic := '0'; SIGNAL X_C : std_logic := '0'; SIGNAL X_D : std_logic := '0'; SIGNAL X_Y : std_logic := '0'; BEGIN UUT : tut1 PORT MAP ( A =>X_A, B =>X_B, C =>X_C, D =>X_D, Y =>X_Y ); Declaration Part of Architecture Body Signals of entity testbench

26. signal_A: process begin X_A <= NOT X_A; wait for 1 ns; end process; signal_B: process begin X_B <= NOT X_B; wait for 2 ns; end process; signal_C: process begin X_C <= NOT X_C; wait for 4 ns; end process; signal_D: process begin X_D <= NOT X_D; wait for 8 ns; end process; END testbench_arch; signal_A signal_B signal_C signal_D