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Lecture #6 Page 1 Lecture #6 Agenda 1.VHDL - Architecture 2.VHDL - Packages Announcements 1.HW #3 assigned ECE 4110– Sequential Logic Design.

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Presentation on theme: "Lecture #6 Page 1 Lecture #6 Agenda 1.VHDL - Architecture 2.VHDL - Packages Announcements 1.HW #3 assigned ECE 4110– Sequential Logic Design."— Presentation transcript:

1 Lecture #6 Page 1 Lecture #6 Agenda 1.VHDL - Architecture 2.VHDL - Packages Announcements 1.HW #3 assigned ECE 4110– Sequential Logic Design

2 Lecture #6 Page 2 VHDL Constructs Systems in VHDL - Systems need to have two things described 1) Interface (I/O, Ports…) 2) Behavior ( Functionality, Structure) - In VHDL, we do this using entity and architecture Entity - used to describe a system's interface - we call the Inputs and Outputs "Ports" - creating this in VHDL is called an "Entity Declaration" Architecture - used to describe a system's behavior (or structure) - separate from an entity - an architecture must be tied to an entity - creating this in VHDL is called an "Architecture Definition" adder.vhd entity declaration architecture definition

3 Lecture #6 Page 3 VHDL Entity Review Entity Syntax Review entity entity-name is port (signal-name : mode signal-type; signal-name : mode signal-type; signal-name : mode signal-type); end entity entity-name; ex) entity adder is port (In1, In2 : in bit; Out1 : out bit); end entity adder; In1 Out In2 Adder

4 Lecture #6 Page 4 VHDL Architecture Architecture Details - an architecture is always associated with an entity (in the same file too) - an architecture definition must possess the following: 1) architecture-name - user selected, different from entity - we usually give something descriptive (adder_arch, and2_arch) - some companies like to use "behavior", "structural" as the names 2) entity-name - the name of the entity that this architecture is associated with - must already be declared before compile 3) optional items… - types - signals : internal connections within the architecture - constants - functions : calling predefined blocks - procedures : calling predefined blocks - components : calling predefined blocks 4) end architecture - keywords to signify the end of the definition - we follow this by the architecture name and ";"

5 Lecture #6 Page 5 VHDL Architecture Architecture Syntax architecture architecture-name of entity-name is type… signal… constant… function… procedure… component… begin …behavior or structure end architecture architecture-name; NOTE: - the keywords are architecture, of, is, type…component, begin, end - there is a ";" at the end of the last line

6 Lecture #6 Page 6 VHDL Architecture Architecture definition of an AND gate architecture and2_arch of and2 is begin Out1 <= In1 and In2; end architecture and2_arch; Architecture definition of an ADDER architecture adder_arch of adder is begin Out1 <= In1 + In2; end architecture adder_arch; In1 Out In2 Adder

7 Lecture #6 Page 7 VHDL Packages VHDL is a "Strong Type Cast" language… - this means that assignments between different data types are not allowed. - this means that operators must be defined for a given data types. - this becomes important when we think about synthesis ex) string + real = ??? - can we add a string to a real? - what is a "string" in HW? - what is a "real" in HW? - VHDL has built-in features: 1) Data Types 2) Operators - built-in is also called "pre-defined"

8 Lecture #6 Page 8 VHDL Packages Pre-defined Functionality ex) there is a built in addition operator for integers integer + integer = integer - the built-in operator "+" works for "integers" only - it doesn't work for "bits" as is Adding on Functionality - VHDL allows us to define our own data types and operators - a set of types, operators, functions, procedures… is called a "Package" - A set of packages are kept in a "Library"

9 Lecture #6 Page 9 VHDL Packages IEEE Packages - when functionality is needed in VHDL, engineers start creating add-ons using Packages - when many packages exist to perform the same function (or are supposed to) keeping consistency becomes a problem - IEEE publishes "Standards" that give a consistent technique for engineers to use in VHDL - we include the IEEE Library at the beginning of our VHDL code syntax: library library-name - we include the Package within the library that we want to use syntax: use library-name.package.function - we can substitute "ALL" for "function" if we want to include everything

10 Lecture #6 Page 10 VHDL Packages Common IEEE Packages - in the IEEE library, there are common Packages that we use: STD_LOGIC_1164 STD_LOGIC_ARITH STD_LOGIC_SIGNED Ex)library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_SIGNED.ALL; - libraries are defined before the entity declaration

11 Lecture #6 Page 11 VHDL Design Let's Put it all together now… library IEEE; -- package use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_SIGNED.ALL; entity and2 is-- entity declaration port (In1, In2: in STD_LOGIC; Out1: out STD_LOGIC); end entity and2; architecture and2_arch of and2 is -- architecture definition begin Out1 <= In1 and In2; end architecture and2_arch;

12 Lecture #6 Page 12 VHDL Design Another Example… library IEEE; -- package use IEEE.STD_LOGIC_1164.ALL; entity inv1 is-- entity declaration port (In1: in STD_LOGIC; Out1: out STD_LOGIC); end entity inv1; architecture inv1_arch of inv1 is -- architecture definition begin Out1 <= not In1; end architecture inv1_arch; The Pre-defined features of VHDL are kept in the STANDARD library - but we don't need to explicitly use the STANDARD library, it is automatic

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