1. Generic Multiplexers: Parameters Discussion D2.5 Example 8

2. A Generic 2-to-1 MUX -- Example 8a: Generic 2-to-1 MUX using a parameter library IEEE; use IEEE.STD_LOGIC_1164.all; entity mux2g is generic (N:integer); port ( a: in STD_LOGIC_VECTOR(N-1 downto 0); b: in STD_LOGIC_VECTOR(N-1 downto 0); s: in STD_LOGIC; y: out STD_LOGIC_VECTOR(N-1 downto 0) ); end mux2g; architecture mux2g of mux2g is begin process(a, b, s) begin if s = '0' then y <= a; else y <= b; end if; end process; end mux2g;

3. -- Example 8b: 8-line 2-to-1 MUX using a parameter library IEEE; use IEEE.STD_LOGIC_1164.all; entity mux28 is port( s : in STD_LOGIC; a : in STD_LOGIC_VECTOR(7 downto 0); b : in STD_LOGIC_VECTOR(7 downto 0); y : out STD_LOGIC_VECTOR(7 downto 0) ); end mux28; architecture mux28 of mux28 is component mux2g generic( N : integer); port( a : in std_logic_vector((N-1) downto 0); b : in std_logic_vector((N-1) downto 0); s : in std_logic; y : out std_logic_vector((N-1) downto 0)); end component;

4. N = 8 begin M8 : mux2g generic map( N => 8 ) port map( a => a, b => b, s => s, y => y ); end mux28;

5. Aldec Active-HDL Simulation