1. http://www.eet.bme.hu Budapest University of Technology and Economics Department of Electron Devices Microelectronics, BSc course Field effect transistors 2: The MOSFETs http://www.eet.bme.hu/~poppe/miel/en/12-MOSFET1.ppt

2. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 2 The abstraction level of our study: SYSTEM MODULE + GATE CIRCUIT n+ SD G DEVICE V out V in

3. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 3 Field effect transistors 1 ► FET = Field Effect Transistor – the flow of charge carriers is influenced by electric field transversal field is used to control Channel JUNCTION FET: depletion layers of pn- junctions close the channel ► Unipolar device: current is conducted by majority carriers ► Power needed for controlling the device  0 Most important parameter: U 0 pinch-off voltage Flow depletion layer

4. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 4 Field effect transistors 2 ► MOSFET: Metal-Oxide-Semiconductor FET First type: depletion mode device Most important parameter: U 0 pinch off voltage - Bulk Second type: enhancement mode device Most important parameter: V T threshold voltage Most frequently used today + depletion layer oxide inversion layer oxide

5. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 5 Field effect transistors 3 ► Symbols: n channel p channel n channel enhancement mode p channel enhancement mode p channel depletion mode n channel depletion mode p channel depletion mode n channel enhancement mode

6. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 6 MOSFETs ► More realistic cross-sectional view of enhnacement mode MOSFETs: Gate oxide n+ SourceDrain p substrate Bulk contact p+ stopper Field-Oxide (SiO 2 ) n+ Polysilicon Gate

7. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 7 The most modern MOSFETs: ► 2007/2008 … Intel:

8. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 8 How is it manufactured?

9. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 9 Poli-Si gate self-aligned device PSG metallization, contact window thin oxideSource/drain dopingpoli-Si gate Structure: Layout: L W

10. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 10 Steps of the self-aligned poli-Si gate process 1) Open window for the active region M  photolitography, field oxide etching 2) Growth of thin oxide 3) Window for hidden contacts M  Contacts the poli-Si gate (yet to be deposited) with the active region (after doping). 3) Deposit poli-Si 4) Patterning of poli-SiM 5) Open window through the thin oxide (etching only)

11. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 11 Steps of the self-aligned poli-Si gate process 6) n+ doping: Form source and drain regions as well as wiring by diffusion lines. Through the hidden contact poli-Si gate will also be connected to diffused lines. 7) Deposit phosphor-silica glass (PSG) as insulator 8) Open contact windows through PSG-n M 9) Metallization 10) Patterning metallization layerM

12. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 12 Metal gate MOS transistor In-depth structure: Layout view: Thin oxide Drain doping Source doping Gate Drain contact Source Problems: metal gate – large V T requires accurate mask alignment

13. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 13 Poly-Si gate MOS transistor In-depth structure: Layout view: thin oxide Drain doping Source doping Gate Drain contact Source Advantages smaller V T self alignment

14. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 14 A poli-Si gate-es nMOS process ► Start with: p type substrate (Si wafer) cleaing, grow thick SiO 2 – this is called field oxide

15. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 15 expose to UV light through a mask, The poli-Si gate nMOS process ► Create the active zone with photolithography coat with resist, development, removal of exposed resists etching of SiO 2 removal of the resist M1: active zone

16. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 16 etch poly-Si, The poli-Si gate nMOS process ► Create the gate structure: pattern poly-Si with photolithography growth of thin oxide deposit poly-Si (resist, exposure,develop) etch thin oxide M2: poly-Si pattern

17. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 17 The poli-Si gate nMOS process ► S/D doping (implantation) the exide (thin, thick) masks the dopants this way the self-alignment of the gate is assured ► Passivation: deposit PSG

18. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 18 The poli-Si gate nMOS process ► Open contact windows through PSG photolithography (resist, etching (copy the pattern) M3: contact window pattern expose pattern,develop) cleaning

19. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 19 The poli-Si gate nMOS process ► Metallization Deposit Al photolithography, M4: metallization pattern etching, cleaning ► The recepy of the process is given, the in-depth structure is determined by the sequence of the masks ► One needs to specify the shapes on the masks  The set of shapes on subsequent masks is called layout

20. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 20 Layout of a depletion mode inverter ► Layout == set of 2D shapes on subsequent masks ► Masks are color coded:  active zone: red  poly-Si: green  contact windows:black  metal:blue ► Mask == layout layer S G D S G D Where is a transistor? Channel between two doped regions: CHANNEL = ACTIVE AND POLY

21. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 21 Further topics: ► Overview of operation of MOS transistors ► Characteristics ► Secondary effects ► Models

22. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 22 Operation of MOSFETs ► The simplest (logic) model:  open (off) / short (on) Gate Source (of carriers) Drain (of carriers) | V GS | | V GS | < | V T | | V GS | > | V T | Open (off) (Gate = ‘0’) Closed (on) (Gate = ‘1’) R on open short enhancement mode device

23. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 23 Operation of MOSFETs ► n-channel device:  electrons are flowing ► p-channel device:  holes are flowing  same operation, change of the signs ► Normally OFF device: at 0 gate (control) voltage the are "open" (enhancement mode device) ► Normally ON device: at 0 gate (control) voltage the are "short" (depletion mode device)

24. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 24 Overview of MOSFET types

25. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 25 Overview of the operation  As a result of electrical field perpendicular to the gate surface positive charges accumulate at the metal (gate) in the p-type semiconductor –first the positive charges are "swept" out and a depletion layer is formed –further increasing the electric field, negative carriers are collected from the bulk under the metal –if the voltage at the surface exceeds a threshold value, the type of the semiconducter gets "inverted": an inversion layer is formed  V T threshold voltage – the minimal voltage needed to form the inversion layer; depends on: the energy levels of the semiconductor material the thickness and the dielectric constant of the oxide (SiO 2 ) the doping level and dielectric constant of the semiconductor (Si) ► The operation is based on the so called MOS capacitance:

26. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 26 Overview of the operation ► Surface phenomena in case of the MOS capacitance Strong inversion: U F = 2  F Accumulation Depletion Inversion

27. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 27 The MOS transistor ► MOS capacitance completed by two electrodes at its two sides: ► n-channel device: current conducted by electrons ► p-channel device: current conducted by holes

28. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 28 Qualitative operation of the MOSFET ► If V GS > V T, inversion layer is formed  the electrons drifted there are all sank in the n+ region and the circuit is closed  the n+ region at the source can inject electrons into the inversion channel  the positive potential at the drain induces flow of electrons in the channel,  the positive potential of the drain reverse biases the pn junction formed there

29. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 29 Qualitative operation of the MOSFET  the charge density in channel depends on the V GS voltage  there is a voltage drop in the channel, thus, the thickness of the inversion layer will deminish along the channel  at a given V DSsat saturation voltage the thickness will reach 0, this is the so called pinch-off V DSsat = V GS - V T After this voltage is reached, the MOSFET operates in saturation mode, the drain voltage does not influence the drain current any longer.

30. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 30 Qualitative operation of the MOSFET In the pinch-off region the charge transort takes place by means of diffusion current.

31. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 31 I-V charactersitics output charactersitic: I D =f(U DS ), parameter: U GS input characteristc: I D =f(U GS ) Output characteristic: In saturation: The circuit designer can change the geometry only: the W width and the L length current constant

32. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 32 Example Calculate the saturation current of a MOSFET for U GS =5V if V T =1V, and the geometry a) W= 5μm, L=0.4μm, b) W= 0.8μm, L=5μm ! a) b)b) By changing the W/L ratio the drain current can be changed by orders of magnitude

33. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 33 I-V charactersitics I D (A) V DS (V) X 10 -4 V GS = 1.0V V GS = 1.5V V GS = 2.0V V GS = 2.5V linearsaturation V DSsat = V GS - V T Quadratic dependece nMOS transistor, 0.25um, L d = 10um, W/L = 1.5, V DD = 2.5V, V T = 0.4V cut-off Voltage controlled current source voltage controlled resistor

34. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 34 Overview of the physics: ► Charges and potentials at the surface ► The threshold voltage ► The charateristics ► Secondary effects

35. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 35 Potentials of the MOS structure oxide semiconductor

36. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 36 Potentials of the MOS structure

37. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 37 The threshold voltage of the MOSFET Inversion

38. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 38 The threshold voltage of the MOSFET

39. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 39 The threshold voltage of the MOSFET Bulk constant: Flat-band potential: FBF T V   SBF U  2 2 P 

40. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 40 Data of a MOSFET device: N a = 4  10 15 /cm 3, relative dielectric constant of Si 11,8, az oxidé 3.9, oxide thickness d ox = 0,03  m,  MS = 0,2 V, Q SS is neglected. Calculate the Fermi potential, the oxide capacitance, the bulk constant and the threshold voltage for U SB = 0 V ! Problem

41. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 41 The charactersitics of an enhnacement mode MOSFET Later we shall calculate these! inversion layer saturation triode region

42. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 42 Derivation of the charactersitic U(0) = U GS, U(L) = U GD Q i (U) = Q i [U(x)] inversion layer

43. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 43 Derivation of the charactersitic inversion layer

44. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 44 Derivation of the charactersitic For all regions of operation! inversion layer if

45. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 45 The saturation region For all regions of operation! Saturation: U GD < V T inversion layer

46. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 46 Overview of all types of MOSFETs

47. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 47 Like an enhance mode MOSFET with a negative threshold voltage Depletion mode MOSFET

48. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 48 Capacitances of the MOSFET Bulk S/D – B capacitance: reverse biased PN junction inversion layer

49. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 49 The gate capacitance: t ox n + n + Cross section L Gate oxide x d x d L d Polysilicon gate Top view Gate-bulk overlap Source n + Drain n + W

50. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 50 Secondary effects ► Channel length reduction ► Narrow channel operation ► Temperature dependence ► Subthreshold current

51. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 51 Dependence of threshold voltage on geometry Short channel: V T decreases Narrow channel: V T increases

52. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 52 Velocity saturation ► Influences the operation of short channel devices In a L = 0.25  m channel device a few Volts of D-S voltage may already result in velocity saturation. Velocity saturation the speed of carriers (due to the collisions) becomes constant  (V/  m)  n (m/s)  sat =10 5 Constant velocity constant mobility (slope =  ) c= c= 5

53. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 53 Velocity saturation ► In short channel device velocity saturation takes place sooner (at lower voltage) IDID Long channel devices Short channel devices V DSAT V GS -V T V GS = V DD VDSVDS

54. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 54 Short channel charactersitics I D (A) V DS (V) X 10 -4 V GS = 1.0V V GS = 1.5V V GS = 2.0V V GS = 2.5V Linear dependence Early velocity saturation LinearSaturation nMOS transistor, 0.25um, L d = 10um, W/L = 1.5, V DD = 2.5V, V T = 0.4V

55. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 55 Temperature dependence

56. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 56 Subthreshold current ► Assuming a given V T is rough model; in reality the current vanishes exponentially with the gate voltage: I D (A) V GS (V) 10 -12 10 -2 subthreshold, exponential region quadratic region linear region VTVT I D ~ I S e (qV GS /nkT) where n  1

57. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 57 Subthreshold current ► Continuous transition between the ON and OFF states  Subthreshold is undesired: strong deviation from the switch model ► I 0, n – empirical parameters, n is typically 1.5 ► Slope factor: S = n (kT/q) ln (10) (tipically: 60..100 mV/decade) – the smaller the better, depends on. Can be reduced by SOI: SiO 2 Si Si substrate e.g. SIMOX process

58. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 58 Subthreshold I D (V GS ) charactersitic V DS : 0.. 0.5V

59. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 59 Subthreshold I D (V DS ) charactersitic V GS : 0.. 0.3V

60. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 60 MOS transistor models ► Neded for circuit simulators (SPICE, TRANZ-TRAN, ELDO, SABER, stb) ► Different levels of complexity:  level0, 1, 2,...n,  EKV,  BSIM3, BSIM4

61. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 61 Examples for MOSFETs Micro-photograph by SEM Photograph by optical microscope S G D inversion layer

62. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 62 Some more complex MOS circuits n- & p-channel devices : CMOS circuit, see later

63. Budapest University of Technology and Economics Department of Electron Devices 25-10-2010 Microelectronics BSc course, The MOSFETs © András Poppe & Vladimír Székely, BME-EET 2008 63 Some more complex MOS circuits Designed by CAD tools