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1 ELEC 422 Applied Integrated Circuit Design Section 2: MOS Fundamentals Chuping Liu [Adapted from Rabaey’s Digital Integrated Circuits, ©2003, J. Rabaey.

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Presentation on theme: "1 ELEC 422 Applied Integrated Circuit Design Section 2: MOS Fundamentals Chuping Liu [Adapted from Rabaey’s Digital Integrated Circuits, ©2003, J. Rabaey."— Presentation transcript:

1 1 ELEC 422 Applied Integrated Circuit Design Section 2: MOS Fundamentals Chuping Liu [Adapted from Rabaey’s Digital Integrated Circuits, ©2003, J. Rabaey et al., and Gaudet’s lecture notes]

2 2 Review of Basic Circuit Theory OUTLINE

3 3 Basic Circuit Elements  Resistor (Unit: Ohm) l Heat Dissipater  Capacitor (Unit: Farad) l Charge Storage  Inductor (Unit: Henry) l High Frequency Blocker

4 4 Resistance of Material Ohmic Law Resistors in Series Resistors in Parallel Resistance and Ohmic Law +V I R

5 5 Capacitance +V I C Capacitance of Material Current Behavior Capacitors in Series Capacitors in Parallel

6 6 Inductance +V I L Current Behavior assuming no mutual interaction, Inductors in Series Inductors in Parallel

7 7 Kirchhoff’s Law  Voltage l For a closed circuit, the total voltage drops at each elements should add up to the voltage applied to the circuit;  Current l For any node in a circuit, the total currents entering the node should add up to those leaving the node.

8 8 PN Junction OUTLINE

9 9 Silicon  IVA element in periodic table  Four outer shell electrons  Four bonds formed in Si crystal (tetragonal structure) 3D tetragonal structure 2D planar schematic

10 10 Doping  The intrinsic charge carrier concentrations is very low in silicon (semiconductor), leading to high resistivity, which could not be used in circuit. To increase charge carrier concentrations, doping with impurities is necessary.  For semiconductor, there’re two ways to dope l if doped with impurity element P (phosphorus), with 5 outer shell electrons, the crystal will have excessive electrons, since only 4 electrons of each atom are used to form bonds. 1 phosphorus atom -> 1 free electron  n-type l If doped with Al (aluminum, 3 outer shell electrons) -> spare sites for electrons, called holes 1 aluminum atom -> 1 free hole  p-type

11 11 PN Junction  PN junctions consist of two semiconductor regions of opposite type. Such junctions show a pronounced rectifying behavior. They are also called abrupt junction.  The PN junctions are versatile elements. They can be used in the following area: l Rectifier, isolation structure and voltage-dependent capacitor. l Solar cells, photodiodes, light emitting diodes and even laser diodes. l Essential part of Metal-Oxide-Silicon Field-Effects- Transistors (MOSFETs) and Bipolar Junction Transistors (BJTs).

12 12 PN Junction p-Si n-Si Before contact, holes and electrons are evenly distributed in p-Si and n-Si respectively. hole still charge electron

13 13 PN Junction pn after some recombination

14 14 PN Junction after fully recombination Depleted Region or Space Charge Region pn

15 15 Built-in Potential in Depletion Region

16 16 Built-in Potential l  0 – the built-in potential l  T – the thermal voltage l N A – the acceptor concentrations in p-materials l N D – the donor concentrations in n-materials l n i – the intrinsic carrier concentration in a pure sample of the semiconductor. (≈1.5x10 10 cm -3 at 300K for silicon) l q – electron charge l k – Boltzman constant

17 17 Built-in Potential Example 3.1 Built-in Voltage of pn-junction An abrupt junction has doping densities of N A =10 15 atoms/cm 3, and N D =10 16 atom/cm 3. Calculate the built-in potential at 300K.

18 18 The Diodes OUTLINE

19 19 The Diode Mostly occurring as parasitic element in Digital ICs

20 20 Diode Current – the ideal diode equation  I S represents a constant value called the saturation current of the diode.  I S is proportional to the area of the diode, and a function of the doping levels and widths of the neutral regions

21 21 Diode Current – Example 3.2  Assume V S =3V, R S =10kΩ, and I S =0.5x10 -16.  V S -R S I D =V D  I D =0.224mA, V D =0.757V I D =0.23mA, V D =0.7V

22 22 Secondary Effects –25.0–15.0–5.05.0 V D (V) –0.1 I D ( A ) 0.1 0 0 Avalanche Breakdown

23 23 OUTLINE The MOS Transistor

24 24 What is a Transistor? A Switch! |V GS | An MOS Transistor

25 25 The MOS Transistor Layout PolysiliconAluminum

26 26 MOS Transistors - Types and Symbols D S G D S G G S D NMOS Enhancement NMOS PMOS Depletion Enhancement D S GB NMOS with Bulk Contact

27 27 The NMOS Transistor Cross Section n areas have been doped with donor ions (arsenic) of concentration N D - electrons are the majority carriers p areas have been doped with acceptor ions (boron) of concentration N A - holes are the majority carriers Gate oxide n+ SourceDrain p substrate Bulk (Body) p+ stopper Field-Oxide (SiO 2 ) n+ Polysilicon Gate L W

28 28 Switch Model of NMOS Transistor Gate Source (of carriers) Drain (of carriers) | V GS | | V GS | < | V T | | V GS | > | V T | Open (off) (Gate = ‘0’) Closed (on) (Gate = ‘1’) R on

29 29 Switch Model of PMOS Transistor Gate Source (of carriers) Drain (of carriers) | V GS | | V GS | > | V DD – | V T | || V GS | < | V DD – |V T | | Open (off) (Gate = ‘1’) Closed (on) (Gate = ‘0’) R on

30 30 Threshold Voltage Concept S D p substrate B G V GS + - n+ depletion region n channel The value of V GS where strong inversion occurs is called the threshold voltage, V T

31 31 The Threshold Voltage V T = V T0 +  (  |-2  F + V SB | -  |-2  F |) where V T0 is the threshold voltage at V SB = 0 and is mostly a function of the manufacturing process V SB is the source-bulk voltage  F = -  T ln(N A /n i ) is the Fermi potential (  T = kT/q = 26mV at 300K is the thermal voltage; N A is the acceptor ion concentration; n i  1.5x10 10 cm -3 at 300K is the intrinsic carrier concentration in pure silicon)  is the body-effect coefficient

32 32 The Body Effect V SB (V) V T (V) l V SB is the substrate bias voltage (normally positive for n-channel devices with the body tied to ground) l A negative bias causes V T to increase from 0.45V to 0.85V

33 33 Transistor in Linear Mode S D B G n+ Assuming V GS > V T and V DS  V GS – V T V GS V DS IDID x V(x) -+ The current is a linear function of both V GS and V DS

34 34 Voltage-Current Relation: Linear Mode For long-channel devices (L > 0.25 micron)  When V DS  V GS – V T I D = k’ n W/L [(V GS – V T )V DS – V DS 2 /2] where k’ n =  n C ox =  n  ox /t ox = is the process transconductance parameter (  n is the carrier mobility (m 2 /Vsec)) k n = k’ n W/L is the gain factor of the device For small V DS, there is a linear dependence between V DS and I D, hence the name resistive or linear region

35 35 Transistor in Saturation Mode S D B G V GS and V DS > V GS - V T IDID V GS - V T -+ n+ Pinch-off Assuming V GS > V T V DS The current remains constant (saturates).

36 36 Voltage-Current Relation: Saturation Mode For long channel devices  When V DS  V GS – V T I D ’ = k’ n /2 W/L [(V GS – V T ) 2 ] since the voltage difference over the induced channel (from the pinch-off point to the source) remains fixed at V GS – V T  However, the effective length of the conductive channel is modulated by the applied V DS, so I D = I D ’ (1 + V DS ) where is the channel-length modulation (varies with the inverse of the channel length)

37 37 Effects on Current  For a fixed V DS and V GS (> V T ), I DS is a function of l the distance between the source and drain – L l the channel width – W l the threshold voltage – V T l the thickness of the SiO 2 – t ox l the dielectric of the gate insulator (SiO 2 ) –  ox l the carrier mobility -for NMOS:  n = 500 cm 2 /V-sec -for PMOS:  p = 180 cm 2 /V-sec I D = k’ n W/L [(V GS – V T )V DS – V DS 2 /2]

38 38 I-V Plot (NMOS) I D (A) V DS (V) X 10 -4 V GS = 1.0V V GS = 1.5V V GS = 2.0V V GS = 2.5V LinearSaturation V DS = V GS - V T Quadratic dependence NMOS transistor, 0.25um, L d = 10um, W/L = 1.5, V DD = 2.5V, V T = 0.4V cut-off

39 39 I-V Plot (PMOS) I D (A) V DS (V) X 10 -4 V GS = -1.0V V GS = -1.5V V GS = -2.0V V GS = -2.5V PMOS transistor, 0.25um, L d = 0.25um, W/L = 1.5, V DD = 2.5V, V T = -0.4V l All polarities of all voltages and currents are reversed

40 40 The MOS Current-Source Model V T0 (V)  (V 0.5 ) V DSAT (V)k’(A/V 2 ) (V -1 ) NMOS0.430.40.63115 x 10 -6 0.06 PMOS-0.4 -30 x 10 -6 -0.1 SD G B IDID I D = 0 for V GS – V T  0 I D = k’ W/L [(V GS – V T )V min –V min 2 /2](1+ V DS ) for V GS – V T  0 with V min = min(V GS – V T, V DS, V DSAT ) l Determined by the voltages at the four terminals and a set of five device parameters

41 41 Summary of MOSFET Operating Regions  Strong Inversion V GS > V T l Linear (Resistive) V DS < V DSAT l Saturated (Constant Current) V DS  V DSAT  Weak Inversion (Sub-Threshold) V GS  V T l Exponential in V GS with linear V DS dependence

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