1. A 2-GHz Direct Sampling ΔΣ Tunable Receiver with 40-GHz Sampling Clock and on-chip PLL T. Chalvatzis 1, T. O. Dickson 1,2 and S. P. Voinigescu 1 1 University of Toronto, Toronto, CA 2 now with IBM T.J. Watson Research Center, NY, USA

2. Outline of Presentation Motivation Circuit design –Loop filter –PLL Measurement results Summary

3. Motivation Direct sampling receiver for 2-GHz radio with 60 MHz BW –CT BP ΔΣ ADC with SNDR of 55dB/60MHz [Chalvatzis et al., JSSC, May 2007] –Investigation of clock jitter impact with on-chip clock source

4. System Architecture 2-GHz Gm-LC BPF Fourth order loop 1-bit quantizer as DFF with F CLK =40GHz RZ pulse DACs 40-GHz VCO/PLL

5. System Level Design Design methodology in continuous-time System level simulation for accurate analysis of loop delay Loop coefficients: –Gm1=22mS, Gm2=15mS –Gfb1=50mS, Gfb2=150mS SNDR=61dB over 60 MHz in Matlab Simulink

6. SNR vs clock jitter Clock jitter effect simulated for F S =40GHz, OSR=333 PLL jitter < 1.4 ps (rms) for 10 bits resolution Δ: quantizer step [Ortmanns et al., ISCAS 2003]

7. SNR vs resonator Q Quantization noise integrated over BW for F S =40GHz Q >18 for 10 bits resolution

8. Loop Filter MOS-HBT cascode for high linearity and low noise EF limit voltage headroom, current source adds noise Loop filter with EF

9. Modified Loop Filter MOS-HBT cascode for high linearity and low noise EF limit voltage headroom, current source adds noise Modified Loop Filter

10. D/A Converter – Quantizer DAC and quantizer with MOS-HBT cascodes [Chalvatzis et al., JSSC, May 2007] MOS on clock path to improve speed with low supply HBT on data path for high gain DAC Latch

11. Digital Receiver – PLL Blocks 40-GHz PLL design from 2.5V challenging Combination of MOS-HBT transistors in PLL blocks Resettable Latch

12. Digital Receiver – PLL Blocks 40-GHz PLL design from 2.5V challenging Combination of MOS-HBT transistors in PLL blocks Charge Pump

13. VCO Colpitts VCO topology with HBT [Dickson et al., CSICS 2006] VCO biased for minimum phase noise Differential tuning with accumulation mode MOS varactors

14. Fabrication and characterization of digital receiver

15. Fabrication ADC with on chip VCO/PLL in STM 0.13μm SiGe BiCMOS Power dissipation 2.19W from 2.5V Chip size 1.59x2.39mm 2 ADC PLL SEL RF IN DIGITAL OUT PLL REF

16. Phase noise/jitter measured on PLL test structure RMS jitter: σ t =849fs Jitter limited SNR for F o =2GHz and OSR=333 -> SNR=66.7dB PLL measurements

17. Phase noise < -103dBc/Hz at 1 MHz offset from 40-GHz carrier VCO measurements

18. Spectrum measurement with PLL ADC tested with external and on-chip clock No significant degradation from on-chip clock Feedthrough from 2.5GHz PLL reference does not degrade performance

19. SFDR measurement SFDR=59dB

20. SNDR measurement SNDR measured for F IN =2GHz, FS=40GHz SNDR = 59.8dB over 60 MHz

21. Dynamic Range ADC noise floor the same (-65dBm/60MHz) when external and on-chip clock employed

22. Digital Receiver Performance Fo2GHz Fs40GHz BW60MHz SNDR59.8dB ENOB9.65bits SFDR59dB P 1dB -2.8dBm DR58.5dB Power2.19W FoM 65.5GHz/W 15.3pJ/bit

23. Conclusion First mm-wave sampling ΔΣ digital receiver in any semiconductor technology Digital receiver achieves 9.65-bit resolution over 60 MHz Removing EF pair in filter helps to increase linearity of ADC loop filter For 10-bits resolution, jitter from on-chip VCO/PLL not limiting performance Noise floor set by resonator Q

24. Acknowledgements Nortel Networks for funding support John Ilowski and Eric Gagnon for discussions STMicroelectronics for chip fabrication Prof Miles Copeland for advice on the manuscript Ricardo Aroca for help with testing CMC for CAD tools Jaro Pristrupa for CAD support