1. Chapter 1 Nanoelectronics Emerging Research Devices Hsin-Chu, Taiwan August 25, 2004 Jim Hutchby – SRC Chair, Emerging Research Device Technical Working Group

2. 1000 100 10 1 0.1 0.01 0.11 T ox ( Å ) classic scaling V dd ( V ) Vt(V)Vt(V) Gate Length, Lgate(  m) 元件小型化 WIRING W/  GATE t ox /  電壓, V/  n-n- n+n+ source drain L/  xd/xd/ psubstrate, doping  *N A 小型化原則： Gate length: L/  Depletion Width: xd/  Voltage: V/  Oxide: tox/  Wire Substrate:  *NA RESULTS: Higher Density: ~  2 Higher Speed: ~  Power/ckt: ~1/  2 Power Density: ~ Constant

3. Power is an issue 1 1E+03 1E+02 1E+01 1E+00 1E-01 0.01 0.1 Standby Power Density Active Power Density Gate Length (  m) 1E-02 1E-03 1E-04 1E-05 Power (W/cm 2 ) Leff and Vdd 導致 Active Power Density ~ 1.3X/generation Passive Power Density ~ 3X/generationGate Leakage Power Density : 4X/generation

4. Result : CMOS power densities escalate unacceptably 12 10 8 6 1960 CMOS Bipolar 4 2 0 Module Heat (watts/cm 2 ) 1950 1980 1970 蒸氣熨斗 5W/cm 2

5. Gate leakage: 10x/0.2nm

6. u George BourinaoffIntel/SRC u Joe BrewerU. Florida u Toshiro HiramotoTokyo U. u Jim HutchbySRC u Mike Forshaw UC London u Tsu-Jae King UC Berkeley u Rainer WaserRWTH A u In YooSamsung u John CarruthersOGI u Joop BruinesPhilips u Jim ChungCompaq u Peng FangAMAT u Dae Gwan KangHynix u Makoto Yoshimi Toshiba u Kristin De MeyerIMEC u Tak Ning IBM u Philip WongIBM u Luan TranMicron u Victor ZhirnovSRC/NCSU u Ramon CompanoEurope Com u Simon Deleonibus LETI u Thomas Skotnicki ST Me u Yuegang ZhangIntel u Kentaro Shibahara Hiroshima U. u Byong Gook ParkSeoul N. U. PIDS Research Devices Working Group Participants Where are TW’s experts?

7. Emerging Research Devices Introduction and Scope Cast a broad net to introduce readers to device and architecture concepts for information processing --- Concept Identify Include Stimulate --- not hardened solutions --- not endorse --- and quantify (new) --- and assess/critique (new)

8. Emerging Research Devices Introduction and Scope Broadened Scope Compared to 2001 Chapter --- New quantitative performance metrics Provide in-depth critical assessment --- key application driven questions/issues --- potential versus to-date performance

9. Scaling Limit of Charge Based Switch An Example of Critical Assessment Observations u Transistor critical dimension limited to ~ 1 nm (In the 2003 ITRS physical gate length = 7 nm for 2018) u Power density, not critical dimension, limits gate density to ~ 1 x 10 9 gates/cm 2 u For the ITRS density and switching time, CMOS is approaching the maximum power efficiency

10. Non-classical CMOS Emerging Research Devices Organization & Component Tasks (2003) Emerging Research Devices Research Logic and Memory Devices Functional Organization (Architectures)

11. Scope of Emerging Research Devices Bulk CMOS Double-Gate CMOS Quantum cellular automataMolecular devices Nanotubes Emerging Information Processing Concepts New Memory and Logic Technologies New Architecture Technologies

12. CMOS Scaling Challenges

13. Bulk-Si Performance Trends Maintaining historical CMOS performance trend requires new semiconductor materials and structures by 2008-2010... Earlier if current bulk-Si data do not improve significantly. “Best Case” : Projected forward MIT Antoniadis

14. Single Gate Non-classical CMOS

15. Multiple Gate Non-classical CMOS

16. Technology Enhancements for High Performance Calculations performed using MASTAR – ST Microelectronics – T. Skotnicki

17. Technology Enhancements for High Performance Calculations performed using MASTAR – ST Microelectronics – T. Skotnicki

18. Scope of Emerging Research Devices Bulk CMOS Double-Gate CMOS Quantum cellular automataMolecular devices Nanotubes Emerging Information Processing Concepts New Memory and Logic Technologies New Architecture Technologies

19. Emerging Research Devices Requirements & Motivations for Beyond CMOS Fundamental Requirements uEnergy restorative functional process (e.g. gain) uCompatible with CMOS uAt or above room temperature operation Compelling Motivations uFunctionally scaleable > 100x beyond CMOS limit uHigh information processing rate and throughput uMinimum energy per functional operation uMinimum, scaleable cost per function

20. 2003 ITRS Emerging Research Devices MEMORY Phase Change Memory Floating body DRAM Nanofloating Gate Memory Single Electron Memory Insulator Resistance Change Memory Molecular Memory LOGIC Rapid Single Flux Quantum Devices 1D structures Resonant Tunneling Devices Single Electron Transistors Molecular devices Quantum Cellular Automata Spin Transistors

21. Emerging Research Memory Devices

22. Memory element Floating body DRAM Charge stored in body of PDSOI MOSFET Nanofloating Gate Memory Flash with engineered tunnel barrier OR charge stored on silicon nano-crystals Single-electron memory Charge stored on a quantum dot channel of an Single Electron Transistor (SET) Capacitor Phase-Change memory - R=f(crystalline - or amorphous - phase) Insulator resistance change Memory R=f(formation/dissolution of metal nanowire?) Molecular Memory R=f(bias voltage) Resistor

23. Floating Body Cell (FBC) of nFET on PD-SOI “1” Write: Operation of the cell in saturation injects holes into the body. “0” Write: Forward-biasing of the pn junction ejects holes from the body. WL(+) BL(+ ) WL(+) BL(- ) (T.Ohsawa et. al.,©ISSCC’02,p.152)

24. Medium-Term Emerging Devices Nano Floating Gate Memory Nanofloating gate memory is evolution of conventional floating gate (FLASH) memory (A) Engineered tunnel barrier n + n + memory node Engineered barrier Si Gate (B) Nanocrystal n + n + Si Gate memory nodes

25. Nanofloating gate memory (NFGM) NFGM includes several possible evolutions of conventional floating gate memory. Graded tunnel barrier –Engineered shape of tunnel barrier Nano-sized memory node –Multiple silicon nanocrystal dots The multiple floating dots are separated and independent, and electrons are injected to the dots via different paths. The endurance problem can be much improved in multidot (nanocrystal) memory

26. The Graded (crested) Barrier Concept Engineered tunnel barriers serve to increase the write/erase performance of memory cells with keeping long retention time typical for floating gate memories. Uses a stack of insulating materials to create a special shape of barrier enabling effective Fowler- Nordheim tunneling into/from the storage node.

27. Nanocrystal Memory Smaller write time –Smaller number of electrons per bit Larger retention time –Prevents discharge through a localized path in defective insulator –Minimizes edge effects Low write voltage –Field enhancement at nanodots Multibit-per-cell storage Improved endurance –Write current density is uniformly distributed along the nanodots –Write current per nanodot is self-limited by Coulomb blockade

28. Tyler Lowrey, Energy Conversion Devices, Inc., http://www.ovonic.com Changes in Resistance I, mA Phase Change Memory

29. Molecular Memory Using individual molecules as building block of memory cells Data are stored by applying external voltage that cause the transition of the molecule into one of two possible phase states. Reading data is performed by measuring resistance changes in the molecular cell It is possible to combine molecular components with existing technology e.g. DRAM and floating gate memory IV Characteristics 1 1 0.000.501.001.502.002.50 3.00 Voltage (V) Current (pA) Source: M.Reed et al - Yale U and Rice U.

30. Factor 1 - - Individual Performance Potential for each Technology Evaluation Criterion 3 Substantially exceeds CMOS * or is compatible with CMOS architecture ** or is monolithically integrable with CMOS wafer technology ***or is compatible with CMOS operating temperature 2 Comparable to CMOS * or can be integrated with CMOS architecture with some difficulty ** or is functionally integrable (easily) with CMOS wafer technology ***or requires a modest cooling technology, T > 77K 1 Substantially (2×) inferior to CMOS * or can not be integrated with CMOS architecture ** or is not integrable with CMOS wafer technology ***or requires very aggressive cooling technology, T < 4K

31. Factor 2 - - Individual Risk Assessment for each Technology Evaluation Criterion 3 Solutions to accomplish most of the Technology Evaluation Criteria for the Technology Entry are known resulting in lowest risk 2 Concepts to accomplish most of the Technology Evaluation Criteria have been proposed for the Technology Entry and are judged to be of moderate risk 1 No solutions or concepts have been proposed accomplish most of the Technology Evaluation Criteria for the Technology Entry and are judged to be of highest risk

32. Overall Performance and Risk Assessment for Technology Entries  Overall Performance and Risk Assessment (OPRA) = Sum [(Performance Potential) x (Risk Assessment)] (Summed over the eight Evaluation Criteria for each Technology Entry)  Maximum Overall Performance and Risk Assessment (OPRA) = 72  Minimum Overall Performance and Risk Assessment (OPRA) = 8

33. Overall Performance and Risk Assessment for Technology Entries Potential for the Technology Entry is projected to be significantly better than silicon CMOS (compared using the Technology Evaluation Criteria) and solutions to accomplish the most of the Technology Evaluation Criteria are known resulting in lowest risk (OPRA > 50) Potential/ Risk Potential for the Technology Entry is projected to be comparable to or slightly less than silicon CMOS (compared using the Technology Evaluation Criteria) and concepts to accomplish most of the Technology Evaluation Criteria have been proposed and are judged to be of moderate risk (OPRA = 40 – 49) Potential/ Risk Potential for the Technology Entry is projected to be comparable to or less than silicon CMOS (compared using the Technology Evaluation Criteria) and concepts to accomplish a few of the Technology Evaluation Criteria have been proposed and are judged to be of higher risk (OPRA = 30 – 39) Potential/ Risk Potential for the Technology Entry is projected to be significantly less than silicon CMOS (compared using the Technology Evaluation Criteria) and no solutions or concepts have been proposed accomplish most of the Technology Evaluation Criteria and are judged to be of highest risk (OPRA < 30) Potential/ Risk

34. Technology Performance and Risk Evaluation Emerging Research Memory Devices Potential/Risk

35. Emerging Research Logic Devices 2003 ITRS PIDS/ERD Chapter

36. Emerging Research Logic Devices Binary decision function u Rapid Single Flux Quantum Devices u Tunneling in superconducting structures u 1D structures u Drift electron transport in nanowires and nanotubes u Resonant Tunneling Devices u Resonant tunneling in semiconductor heterostructures u Single Electron Transistors u Single electron tunneling and coulomb blockade u Molecular devices u Electron transport in molecules u Quantum Cellular Automata u Tunneling u Spin Transistors u Spin transport in transistor structure

37. Rapid Single Flux Quantum  RSFQ logic is a dynamic logic based upon a superconducting quantum effect, in which the storage and transmission of flux quanta defines the device operation.  The basic RSFQ structure is a superconducting ring that contains one Josephson Junction (JJ) plus an external resistive shunt. The storage element is the superconducting inductive ring and the switching element is the Josephson Junction.  RSFQ dynamic logic uses the presence or absence of the flux quanta in the closed superconducting inductive loop to represent a bit as a “ 1 ” or “ 0, ” respectively. The circuit operates by temporarily opening the Josephson Junction, thereby ejecting the stored flux quanta.

38. CNT transistor S. J. Wind,J. Appenzeller, R. Martel, V. Derycke, and Ph. Avouris, Appl. Phys. Lett 80 (2002) 3817 Major Challenges for CNT FETs u What are the ultimate limits to the speed, size, density and dissipated energy of an CNT switch (e.g. FET) switch? u How can 100 or more CNTs be combined in parallel to provide a total current 100x current of a single CNT? u Possibilities for integration of individual CNT components in a complex circuit (billions of components per cm 2 ) are unclear.

39. Single Electron Transistor (SET) u Electron movements are controlled with single electron precision u Coulomb blockade effect u Logic state set by 1) current or 2) phase

40. Quantum Cellular Automata: “Wireless” or Systolic Logic Circuitry? Logic CellAdder Circuit

41. Technology Performance and Risk Evaluation Emerging Research Logic Devices Potential/Risk

42. Emerging Research Logic Devices 2003 ITRS PIDS/ERD Chapter

43. Architecture Non- classical CMOS Memory Logic Risk Emerging Technology Sequence Quasi ballistic FET UTB single gate FET UTB multiple gate FET Floating body DRAM Nano FG SETMolecular Phase change SET RSFQ QCAMolecular Resonant tunneling Quantum computing Defect tolerant Cellular array Source/Drain engineered FET Biologically inspired Emerging Technology Vectors Transport enhanced FETs Spin transistor 1-D structures Insulator resistance change

45. Emerging Research Devices Summary u Potential solutions for device structures necessary to achieve the advanced nodes (< 45-nm) identified u For the ITRS gate density and switching time - v Power density (not switch size) limits charge based logic density and performance v CMOS is approaching the maximum power efficiency u Emerging Research Device Technologies will extend CMOS into new application domains

46. SET-Based Tunneling Phase Logic (TPL) Q 2 2C -e/2e/2 Q E e/2C -e/2C VJVJ q e Coulomb Blockade Nonlinear Voltage-Charge Characteristic U. Minnesota UC - Berkeley Bias ac Pump Tunnel Junction TPL Element