Presentation on theme: "A CCD-based vertex detector Status report from the LCFI collaboration"— Presentation transcript:
1 A CCD-based vertex detector Status report from the LCFI collaboration Konstantin StefanovRALOverview of the LCFI programmeConceptual design of the vertex detector for the future LCDetector R&D program at LCFIDevelopment of very fast CCDs and readout electronicsExperimental studies on a commercial high speed CCDThin ladder programme for mechanical support of the sensorsSummary
2 LCFI Overview Work in two directions: Simulation of CCD-based vertex detector performance using physics processes at the LC (Chris Damerell’s talk)Detector R&D: development of fast CCDs for the vertex detector and their support structurePhysics studies are continuing, but we know that:Many particles in jets with low momentum ( 1 GeV/c) even at high collision energy, multiple scattering still dominant;Very efficient and pure b and c tagging needed;Vertex charge measurement important.
3 Pushing the technology hard… Detector ParametersImpact parameter resolution: , [m]Thin detector (< 0.1% X0) for low error from multiple scatteringClose to the interaction point for reduced extrapolation errorReadout time: 8 ms for NLC/JLC (read between trains)50 s for TESLA (read the inner CCD layer 20 times during the train)Two track separation 40 m, small pixel size 20 m 20 m;Large polar angle coverage;Stand-alone tracking: 4 or 5 layers of sensors;Radiation hard.Pushing the technology hard…
4 Conceptual design 5 layers at radii 15, 26 37, 48 and 60 mm; Gas cooled;Low mass, high precision mechanics;Encased in a low mass foam cryostat;Minimum number of external connections (power + few optical fibres).
5 CCD developmentLarge area, high speed CCD – follows the ideas of the SLD VXD3 designPixel size: 20 m squareInner layer CCDs: 10013 mm2Outer layers: 2 CCDs with size 12522 mm2120 CCDs, 799106 pixels totalReadout time 8 ms in principle sufficient for NLC/JLCFor TESLA: 50 s readout time for inner layer CCDs:50 Mpix/s from EACH CCD columnFuture LC requires different concept for fast readout – Column Parallel CCD (CPCCD)Natural and elegant development of CCD technology
6 Column parallel CCD Serial register is omitted Maximum possible speed from a CCD (tens of Gpix/s)Image section (high capacitance) is clocked at high frequencyEach column has its own amplifier and ADC – requires readout chip“Classic CCD”Readout time NM/FoutNMN+1Column Parallel CCDReadout time = (N+1)/Fout
7 List of issues to be solved: CCD ladder endList of issues to be solved:Bump bonding assembly between thinned CPCCD and readout chipDriving the CPCCD with high frequency low voltage clocks;Driver design;Low inductance connections and layout;Clock and digital feedthrough;Cooling the ladder end.
8 CCD bump-bonded to custom CMOS readout chip with: Amplifier and ADC per columnCorrelated Double Sampling for low noiseGain equalisation between columnsPixel thresholdVariable size cluster finding algorithmData sparsificationMemory and I/O interface
9 Column Parallel CCD Important aspects of CPCCD: Quality of 50 MHz clocks over the entire device (area = 13 cm2):All clock paths have to be studied and optimisedPower dissipation:Pulsed power if necessaryLow clock amplitudesLarge capacitive load (normally 2-3nF/cm2)Feedthrough effects:2-phase drive with sine clocks – natural choice because of symmetry and low harmonicsGround currents and capacitive feedthrough largely cancelMost of these issues are being studied by simulation
10 Charge packet in a 2-phase CCD Device simulationsCharge packet in a 2-phase CCDUsing ISE-TCAD software and SPICE models2D models for:potential profiles;low voltage charge transferfeedthrough studies3-D models being used as wellSPICE simulations of clock propagation
11 Device simulations Extensive simulation work done at RAL; 2D model for standard 2 phase CCD developed;Electric fields and charge transfer times can be calculated;In simulation 50 MHz transfer achieved with 1.5 Vpp clocks – to be compared with real device; Clock propagation over the CCD area largely understood;Will use polysilicon gates (30 /sq) covered with aluminium (0.05 /sq) for high speed.
12 Hybrid assembly CPCCD-CMOS Features in our first CPCCD: 2 different charge transfer regions;3 types of output circuitry;Independent CPCCD and readout chip testing possible:Without bump bonding - use wire bonds to readout chipWithout readout chip - use external wire bonded electronicsDesigned to work in (almost) any case.Standard 2-phaseimplantMetallised gates(high speed)Field-enhanced 2-phase implant (high speed)SourcefollowersDirect2-stagesourceTo pre-ampsReadoutASIC
13 CPCCD designDesigned by E2V (former Marconi Applied Technologies, EEV);Fruitful long-term collaboration: the same people designed the CCDs for VXD2 and VXD3;In production, to be delivered November 2002Several variants:For standalone testing and for bump bonding;With/without gate and bus line shield metallisation;Variable doping, gate thicknessFirst step in a 5 or 6 stage R&D programme.
14 Test readout chip design A comparator using Charge Transfer Amplifier, repeated 31 times per ADCReadout chip designed by the Microelectronics Group at RAL;0.25 m CMOS process;Charge Transfer Amplifiers (CTA) in each ADC comparator;Scalable and designed to work at 50 MHz.CPR-0 : Small chip (2 mm 6 mm) for tests of the flash ADC and voltage amplifiers, already manufactured and delivered, currently being tested;CPR-1 : Contains amplifiers, bit ADCs and FIFO memory in 20 m pitch.
15 Test readout chip design In CPR-1:Voltage amplifiers – for source follower outputs from the CPCCDCharge amplifiers – for the direct connections to the CPCCD output nodesAmplifier gain in both cases: 100 mV for 2000 e- signalNoise below 100 e- RMS (simulated)Direct connection and charge amplifier have many advantages:Eliminate source followers in the CCDReduce power 5 times to 1 mW/channelProgrammable decay time constant (baseline restoration)ADC full range: 100 mV, AC coupled, Correlated Double Sampling built-in (CTA does it)FIFO250 5-bit flash ADCsCharge AmplifiersVoltage AmplifiersWire/bump bond padsBump bond pads
16 Tests of high-speed CCDs E2V CCD583-phase, frame transfer CCD2.1 million pixels in 2 sections12 m square pixelsHigh responsivity: 4 V/electron2 outputs (3-stage source followers)Bandwidth 60 MHzTest bench for high-speed operation with MIP-like signals
17 Tests of high-speed CCDs 55Fe X-ray spectrum at 50 Mpix/s MIP-like signal (5.9 keV X-rays generate 1620 electrons);Low noise 50 electrons at 50 MHz clocks;CCD58 is designed to work with large signals at 10 Vpp clocks;No performance deterioration down to 5 Vpp clocks;Still good even at 3 Vpp clocks.
18 Tests of high-speed CCDs Low drive voltage tests at 50 Mpix/s:Actual clock traces and 55Fe X-ray spectrumRadiation damage effects:Backgrounds: 50 krad/year (e+e- pairs) 109 neutrons/cm2/y (large uncertainty)Radiation damage effects on CCD58 being studied;Radiation-induced CTI should improve a lot at speeds > 5-10 Mpix/s – to be verified;Flexible clocking of CCD58 from MHz to 50 MHz – should be able to get good results;Notes
19 Thin ladder R&DA program to design a CCD support structure with the following properties:Very low mass (< 0.4% X0 – SLD VXD3)Repeatability of the shape to few microns when temperature cycled down to –100 C;Minimum metastability or hysteresis effects;Compatible with bump bonding;Overall assembly sufficiently robust for safe handling with appropriate jigs;Structure must allow use of gas cooling.
20 Thin ladder R&D Three options: Unsupported CCDs – thinned to 50 m and held under tensionSemi-supported CCDs – thinned to 20 m and attached to thin (and not rigid) support, held under tension;Fully-supported CCDs – thinned to 20 m and bonded to 3D rigid substrate (e.g. Be)The first version has been studied experimentally: sagitta stability vs. tension: better than 2 m at tension > 2NTensionCompressionCCD 1CeramicSiliconCCD 2Ladder blockAnnulus blockV and flatsliding joint
21 Semi-supported option currently under study Unsupported siliconAdhesive pulls silicon downSiliconCeramicsAdhesiveButt jointSeveral problems:Large differential thermal contractions at the CCD surface (oxides, passivation, metals) – cause lateral curlingHandling: testing, bump-bonding, etc. very difficultSemi-supported option currently under study
22 Semi-supported silicon CCD (20 μm thin) bonded with adhesive pads to 250 μm Be substrateOn cooling adhesive contracts more than Be pulls Si down on to Be surfaceLayer thickness 0.12% X01 mm diameter adhesive columns inside 2 mm diameter wells 200 μm deep in Be substrate6 m3 mExtensively simulated using ANSYS, a model will be made soonCCD surface may become dimpled – under studyMay need very fine pitch of adhesive pad matrix difficult assembly procedure, weakened substrate, complex non-uniform material profile…
23 Semi-supported structures Carbon fibre supportAerogel supportCarbon fibre: CTE is tunable, layers can have optimal orientation and fibre diameter, difficult to simulateAerogel support: chemically bonds to Si, aerogel in compressionMany other ideas: CVD diamond, vacuum retention, etc…
24 Summary Detector R&D work at the LCFI collaboration is focused on: Development of very fast column parallel CCD and its readout chip;Study the performance of commercial CCDs with MIP-like signals at high speeds and radiation damage effects;Precision mechanical support of thinned CCDs.CCD-based vertex detector for the future LC is challenging, but looks possible;Major step forward from SLD VXD3, significant customisation required;Many technological problems have to be solved;Have to work hard, R&D is extensive and complex;Different versions of the CPCCD likely to find warm welcome in science and technology.More information is available from LCFI’s web page: