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The Status of the LCFI Project Snowmass 2005 Joel Goldstein CCLRC Rutherford Appleton Laboratory For the LCFI Collaboration.

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Presentation on theme: "The Status of the LCFI Project Snowmass 2005 Joel Goldstein CCLRC Rutherford Appleton Laboratory For the LCFI Collaboration."— Presentation transcript:

1 The Status of the LCFI Project Snowmass 2005 Joel Goldstein CCLRC Rutherford Appleton Laboratory For the LCFI Collaboration

2 Joel Goldstein, RALSnowmass05 2 Outline 1.LCFI Research Programme: A. Physics Studies (Sonjas Talk) B. Mechanical Development C. Detector Development

3 Joel Goldstein, RALSnowmass05 3 Baseline Vertex Detector 800 Mchannels of m pixels in 5 layers Optimisation: –Inner radius (1.5 cm?) –Readout time (50 s?) –Ladder thickness (0.1% X 0 ?)

4 Joel Goldstein, RALSnowmass05 4 Mechanical Options Target of 0.1% X 0 per layer (100 m silicon equivalent) 1.Unsupported Silicon –Longitudinal tensioning provides stiffness –No lateral stability –Not believed to be promising 2.Thin Substrates –Detector thinned to epitaxial layer (20 m) –Silicon glued to low mass substrate for lateral stability –Longitudinal stiffness still from tension –Beryllium has best specific stiffness 3.Rigid Structures

5 Joel Goldstein, RALSnowmass05 5 Laser Survey System Laser displacement meter on X-Y stage X-Y precision < 1 µm Z precision ~ 1 µm Ladder in cryostat: –T 100 degC Fast: –1D scan in ~ 30s e.g. during cooling

6 Joel Goldstein, RALSnowmass05 6 Mechanical Studies of Be-Si Physical Prototyping ~160 μm ripples at - 60°C Good qualitative agreement Minimum thickness ~ 0.15% X 0 Tension Silicon detector Glue pillar Beryllium substrate FEA Simulations

7 Joel Goldstein, RALSnowmass05 7 Carbon Fibre Substrates Carbon fibre has better CTE match than beryllium profile of silicon along the length of a ladder Prototype ~ 0.09% X 0 –No rippling down to < 200K –Investigating lateral stability Thin ceramic substrates may also be possible

8 Joel Goldstein, RALSnowmass05 8 Other Thin Substrates Other possibilites with good CTE match: –Ceramics: silicon carbide, boron carbide, alumina… –diamond

9 Joel Goldstein, RALSnowmass05 9 Rigid Structures Prototyping with: –3% RVC –8% SiC No tensioning needed No possibility too crazy…. Foam: substrate or sandwich core

10 Joel Goldstein, RALSnowmass05 10 Silicon Carbide Foam Thin layer of glue Glue pillars

11 Joel Goldstein, RALSnowmass05 11 Global Design Work Ladder end with leaf spring Enough detail for ladder design sanity check

12 Joel Goldstein, RALSnowmass05 12 Sensors: The Challenge What readout speed is needed? Inner layer 1.6 MPixel sensors Once per bunch = 300ns per frame : too fast Once per train ~200 hits/mm 2 : too slow 10 hits/mm 2 => 50μs per frame: just right (Fastest commercial imaging ~ 1 ms/MPixel) Power dissipation – gas volume cooling 337 ns 2820x 0.2 s 0.95 ms Beam Time Structure :

13 Joel Goldstein, RALSnowmass05 13 Column Parallel CCD N+1 Column Parallel CCD Readout time = (N+1)/F out Separate amplifier and readout for each column 50 MHz clock rate

14 Joel Goldstein, RALSnowmass05 14 Column Parallel CCD N+1 Column Parallel CCD Readout time = (N+1)/F out Separate amplifier and readout for each column 50 MHz clock rate Clock drive is real challenge

15 Joel Goldstein, RALSnowmass05 15 Prototype CP CCD CPC1 produced by E2V Two phase operation Metal strapping for clock 2 different gate shapes 3 different types of output 2 different implant levels Clock with highest frequency at lowest voltage

16 Joel Goldstein, RALSnowmass05 16 CPC1 Results Noise ~ 100 electrons (60 after filter) Minimum clock ~1.9 V Maximum frequency > 25 MHz –inherent clock asymmetry Need bumped assemblies to check charge amplifiers

17 Joel Goldstein, RALSnowmass05 17 CP Readout ASIC CPR1 designed by RAL ME Group IBM 0.25μm process 250 parallel channels with 20μm pitch Designed for 50 MHz Data multiplexed out through 2 pads

18 Joel Goldstein, RALSnowmass05 18 Bumped Assemblies Bonding by VTT, Finland Bump yield very high Some whole chip failures –Not yet understood

19 Joel Goldstein, RALSnowmass05 19 Bumping Failures Short between CCD substrate and chip ground Possible mechanical damage

20 Joel Goldstein, RALSnowmass05 20 Testing Results Charge amplifiers work Negligible noise from CPR Column parallel operation demonstrated No signal in ~20% of voltage channels Readout chip very sensitive to timing and bias issues Gain decrease towards centre of chip 6 keV X-rays Voltage Amplifiers (non-inverting) Charge Amplifiers (inverting)

21 Joel Goldstein, RALSnowmass05 21 The Next Generation CCDs –Larger and faster prototypes –Clock drivers –Radiation effects ASICs –More robust –Cluster finding logic Storage Sensors: –Large EM leakage from ILC bunch train –Charge-voltage conversion dangerous –Store multiple charge samples locally –Readout all samples during 200ms dead time

22 Joel Goldstein, RALSnowmass05 22 In-situ Storage Imaging Sensors 1.Charge collection similar to CCD or CMOS 2.Charge transferred into local CCD array every 50μs 3.Local CCD array clocked at 20 kHz 4.Source follower for every pixel 5.Read out one row at a time Still column parallel

23 Joel Goldstein, RALSnowmass05 23 Linear ISIS Orders of magnitude increased resistance to RF Much reduced clocking requirements (readout ~1MHz) Combination of CCD and CMOS technology on small pitch Can it be made? Can we afford it? To column load Source followerReset transistor Row select transistor p+ shielding implant n+ buried channel (n) storage pixel #1 storage pixel #20 sense node (n+) Charge collection row select reset gate V DD p+ well reflected charge photogate transfer gate output gate High resistivity epitaxial layer (p)

24 Joel Goldstein, RALSnowmass Storage gate RSEL OD RD RG OS to column load Storage gate 3 Transfer gate 8 Output gate Output node Photogate Charge generation Transfer Storage Readback from gate 6 Idea by D. Burt and R. Bell (e2V)

25 Joel Goldstein, RALSnowmass05 25 FAPS FAPS architecture –Flexible active pixel sensors –Adds pixel storage to MAPS –Present design* is proof of principle test structure, delivered & tested in 2004 (MIP S/N = ~15) –Pixels 20x20 m 2, 3 metal layers, 10 storage cells *(2-year PPARC funded programme to develop underpinning technology. Started June 2003)

26 Joel Goldstein, RALSnowmass05 26 CPC2 Double metal now available from E2V Symmetric clock design Busline-free option Compatible with old and new readout chips

27 Joel Goldstein, RALSnowmass05 27 Busline Free CCDs Clock signals transmitted via distributed drive planes –Faster propagation –More uniform 1 mm

28 Joel Goldstein, RALSnowmass05 28 CPC-2 Production 92 mm CPCCD2 Dedicated wafers at E2V 3 sizes of CCD sensors Prototype 16×16 pixel ISIS structures

29 Joel Goldstein, RALSnowmass05 29 CPC2 Status Wafers in DC Probing Delivery of single metal devices in next few weeks

30 Joel Goldstein, RALSnowmass05 30 CCD Drivers Clock drivers are a big challenge –Working on air core PCB transformers –Long-term solution more likely to be IC with local storage

31 Joel Goldstein, RALSnowmass05 31 CPR2 New features: –Cluster finding logic and sparse readout –Better uniformity and linearity (improved amplifiers and ADC) –Reduced sensitivity to clock timing and power supply –Reduced noise –Variety of test modes –IBM 0.25µm –Multi-project run (CERN) –Delivered in March

32 Joel Goldstein, RALSnowmass05 32 CPR2 Layout Output Sparsification Cluster Binary 5-bit ADC Preamp Input & Multiplexing Finding Conversion

33 Joel Goldstein, RALSnowmass05 33 CPR2 Testing

34 Joel Goldstein, RALSnowmass05 34 Summary First generation prototypes extensively studied –Column parallel CCD principle proven –Direct charge output demonstrated Two-prong attack for next generation –Detector-scale CCDs, sparsification –In-situ storage devices for RF resistance 0.1% X 0 ladders seem achievable –Carbon fibre and RVC foam most promising Good progress with physics studies Exciting time ahead!

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