1. DLD Lecture 19 Recap II Give qualifications of instructors: DAP
teaching computer architecture at Berkeley since 1977
Co-athor of textbook used in class
Best known for being one of pioneers of RISC
currently author of article on future of microprocessors in SciAm Sept 1995 RY
took 152 as student, TAed 152,instructor in 152
undergrad and grad work at Berkeley
joined NextGen to design fact 80x86 microprocessors
one of architects of UltraSPARC fastest SPARC mper shipping this Fall

2. Recap Number System/Inter-conversion, Complements Boolean Algebra
More Logic Functions: NAND, NOR, XOR
Minimization with Karnaugh Maps
More Karnaugh Maps and Don’t Cares
NAND and XOR Implementations
Circuit Analysis and Design Procedures
Binary Adders and Subtractors
Magnitude Comparators and Multiplexers
Encoders, Decoders and DeMultiplexers

3. It is easier to communicate with computers using formal logic.
Boolean Algebra
Formal logic: In formal logic, a statement (proposition) is a declarative sentence that is either
true(1) or false (0).
It is easier to communicate with computers using formal logic.
Boolean variable: Takes only two values – either
true (1) or false (0).
They are used as basic units of formal logic.

4. Venn Diagrams A B A B A B A B A A School days, base is set theory,
A U B = Everything that is in either of the sets, A n B = only the things that are in both of the set, Ac = everything in the universe outside of  A
Last= Vertical lines representing the Ac while the horizontal lines represent the Bc and they intersect each other outside A and B’s complements area A A

5. Boolean Algebra
Boolean Algebra is a mathematical technique that provides the ability to algebraically simplify logic expressions. These simplified expressions will result in a logic circuit that is equivalent to the original circuit, yet requires fewer gates. A B C
AB+A(B+C)+B(B+C) A B C
B+AC

6. The three basic logical operations are:
AND OR
NOT
AND is denoted by a dot (·).
OR is denoted by a plus (+).
NOT is denoted by an overbar ( ¯ ), a single quote mark (') after, or (~) before the variable.

7. Boolean & DeMorgan’s Theorems
Digital Electronics 
2,1 Introduction to AOI Logic
Boolean & DeMorgan’s Theorems
Commutative Law
Associative Law
Distributive Law
Updates of the Boolean Theorems with the addition of DeMorgan’s
Consensus Theorem
DeMorgan’s
Project Lead The Way, Inc.
Copyright 2009

8. Representation Conversion
Need to transition between boolean expression, truth table, and circuit (symbols).
Converting between truth table and expression is easy.
Converting between expression and circuit is easy.
More difficult to convert to truth table.
Truth
Table
Circuit
Boolean
Expression

10. NAND gates have several interesting properties…
The NAND Gate A Y B
This is a NAND gate. It is a combination of an AND gate followed by an inverter. Its truth table shows this…
NAND gates have several interesting properties…
NAND(a,a)=(aa)’ = a’ = NOT(a)
NAND’(a,b)=(ab)’’ = ab = AND(a,b)
NAND(a’,b’)=(a’b’)’ = a+b = OR(a,b) A B Y 1

11. The NAND Gate
These three properties show that a NAND gate with both of its inputs driven by the same signal is equivalent to a NOT gate
A NAND gate whose output is complemented is equivalent to an AND gate, and a NAND gate with complemented inputs acts as an OR gate.
Therefore, we can use a NAND gate to implement all three of the elementary operators (AND,OR,NOT).
Therefore, ANY switching function can be constructed using only NAND gates. Such a gate is said to be primitive or functionally complete.

12. NAND Gates into Other Gates
(what are these circuits?) A Y Y A B
NOT Gate
AND Gate A B Y
OR Gate

13. Cascaded NAND Gates
3-input NAND gate

14. NAND Gate and Laws

15. NOR gates also have several interesting properties…
The NOR Gate A Y B
This is a NOR gate. It is a combination of an OR gate followed by an inverter. It’s truth table shows this…
NOR gates also have several
interesting properties…
NOR(a,a)=(a+a)’ = a’ = NOT(a)
NOR’(a,b)=(a+b)’’ = a+b = OR(a,b)
NOR(a’,b’)=(a’+b’)’ = ab = AND(a,b) A B Y 1

16. Functionally Complete Gates
Just like the NAND gate, the NOR gate is functionally complete…any logic function can be implemented using just NOR gates.
Both NAND and NOR gates are very valuable as any design can be realized using either one.
It is easier to build an IC chip using all NAND or NOR gates than to combine AND,OR, and NOT gates.
NAND/NOR gates are typically faster at switching and cheaper to produce.

17. NOR Gates into Other Gates
(what are these circuits?) A Y
NOT Gate Y A B
OR Gate A B Y
AND Gate

18. NOR Gate and Laws

19. The XOR Gate (Exclusive-OR)Y B
This is a XOR gate.
XOR gates assert their output
when exactly one of the inputs
is asserted, hence the name.
The switching algebra symbol
for this operation is , i.e.
1  1 = 0 and 1  0 = 1.
Output is high when either A or B is high but not the both A B Y 1

20. simply the complement of the XOR gate. The switching algebra symbol
The XNOR Gate A Y B
This is a XNOR gate.
This functions as an
exclusive-NOR gate, or
simply the complement of
the XOR gate.
The switching algebra symbol
for this operation is , i.e.
1  1 = 1 and 1  0 = 0. A B Y 1

22. K-Maps
Ex: How do you transform a K-map into a truth table? Is it unique? How do you transform a K-map into an n-cube? Is it unique? Two- and Three-Variable Maps

23. Application of Karnaugh Maps: The One-bit Adder
Cin
Cout S B A A B
Cin S
Cout 1 1 1 1 1 1 1 1 1
How to use a Karnaugh
Map instead of the
Algebraic simplification? 1 1 1 1 1 1 1 1 1 1 1 +
S = A’B’Cin + A’BCin’ + A’BCin + ABCin
Cout = A’BCin + A B’Cin + ABCin’ + ABCin
= A’BCin + ABCin + AB’Cin + ABCin + ABCin’ + ABCin
= (A’ + A)BCin + (B’ + B)ACin + (Cin’ + Cin)AB
= 1·BCin + 1· ACin + 1· AB
= BCin + ACin + AB

24. Application of Karnaugh Maps: The One-bit Adder
Cin
Cout S B A A B
Cin 1
Now we have to cover all the 1s in the
Karnaugh Map using the largest
rectangles and as few rectangles
as we can.
Karnaugh Map for Cout

25. Application of Karnaugh Maps: The One-bit Adder
Cin
Cout S B A A B
Cin
Now we have to cover all the 1s in the
Karnaugh Map using the largest
rectangles and as few rectangles
as we can. 1 1 1
Cout = ACin
Karnaugh Map for Cout

26. Application of Karnaugh Maps: The One-bit Adder
Cin
Cout S B A A B
Cin
Now we have to cover all the 1s in the
Karnaugh Map using the largest
rectangles and as few rectangles
as we can. 1 1 1
Cout = Acin + AB
Karnaugh Map for Cout

27. Application of Karnaugh Maps: The One-bit Adder
Cin
Cout S B A A B
Cin
Now we have to cover all the 1s in the
Karnaugh Map using the largest
rectangles and as few rectangles
as we can. 1 1 1
Cout = ACin + AB + BCin
Karnaugh Map for Cout

28. Application of Karnaugh Maps: The One-bit Adder
Cin
Cout S B A A B
Cin 1 1 1 1
S = A’BCin’
Karnaugh Map for S

29. Application of Karnaugh Maps: The One-bit Adder
Cin
Cout S B A A B
Cin 1 1 1 1
S = A’BCin’ + A’B’Cin
Karnaugh Map for S

30. Application of Karnaugh Maps: The One-bit Adder
Cin
Cout S B A A B
Cin 1 1 1 1
S = A’BCin’ + A’B’Cin + ABCin
Karnaugh Map for S

31. Application of Karnaugh Maps: The One-bit Adder
Can you draw the circuit diagrams?
Adder
Cin
Cout S B A A B
Cin 1 1 1 1
S = A’BCin’ + A’B’Cin + ABCin + AB’Cin’
Karnaugh Map for S
No Possible Reduction!

33. Karnaugh Maps for Four Input Functions
Represent functions of 4 inputs with 16 minterms
Use same rules developed for 3-input functions
Note bracketed sections shown in example.

34. Karnaugh map: 4-variable example
F(A,B,C,D) = m(0,2,3,5,6,7,8,10,11,14,15) F =
+ B’D’ C
+ A’BD A A B C D
0000
1111
1000
0111
1 0
0 1
0 0
1 1 C D B
Solution set can be considered as a coordinate
System!

35. Don’t cares
In digital systems it often happens that certain input conditions can never occur.
For example, suppose that x1 and x2 control two interlocked switches such that both switches cannot be closed at the same time. Thus the only three possible states of the switches are that both switches are open or that one switch is open and the other switch is closed.
Namely, the input valuations (x1, x2) = 00, 01, and 10 are possible, but 11 is guaranteed not to occur.
Then we say that (x1, x2) = 11 is a don’t-care condition , meaning that a circuit with x1 and x2 as inputs can be designed by ignoring this condition.
A function that has don’t-care condition(s) is said to be incompletely specified.

36. Karnaugh maps: Don’t cares
In some cases, outputs are undefined
We “don’t care” if the logic produces a 0 or a 1
This knowledge can be used to simplify functions. A AB CD 00 01 11 10 00 01
0 0
1 1
X 0
X 1
- Treat X’s like either 1’s or 0’s
Very useful
OK to leave some X’s uncovered D C 11 10
1 1
0 X
0 0 B

37. Karnaugh maps: Don’t cares
f(A,B,C,D) = m(1,3,5,7,9) + d(6,12,13)
without don't cares
f = A 1 + B 1 + C D 1 f
A’D
+ C’D 1 1 A 1 1 AB CD 00 01 11 10 1 00 01 1 X
0 0
1 1
X 0
X 1 1 1 X D C 11 10
1 1
0 X
0 0 B

38. Don’t Care Conditions
In some situations, we don’t care about the value of a function for certain combinations of the variables.
these combinations may be impossible in certain contexts
or the value of the function may not matter in when the combinations occur
In such situations we say the function is incompletely specified and there are multiple (completely specified) logic functions that can be used in the design.
so we can select a function that gives the simplest circuit
When constructing the terms in the simplification procedure, we can choose to either cover or not cover the don’t care conditions.

39. Map Simplification with Don’t CaresAB x 1 00 01 CD 11 10
F=ACD+B+AC
Alternative covering. AB x 1 00 01 CD 11 10
F=ABCD+ABC+BC+AC

40. Karnaugh maps: don’t cares (cont’d)
f(A,B,C,D) = m(1,3,5,7,9) + d(6,12,13)
f = A'D + B'C'D without don't cares
f = with don't cares
A'D
by using don't care as a "1" a 2-cube can be formed rather than a 1-cube to cover this node
+ C'D
0 0
1 1
X 0
X 1 D A
0 X B C
don't cares can be treated as 1s or 0s depending on which is more advantageous

41. Some You Group, Some You Don’t
Karnaugh Mapping
Digital Electronics
2.2 Intro to NAND & NOR Logic
Some You Group, Some You Don’t
This don’t care condition was treated as a (1). This allowed the grouping of a single one to become a grouping of two, resulting in a simpler term. V X 1
Explain that you include don’t care conditions only if it allows you to make a grouping larger.
There was no advantage in treating this don’t care condition as a (1), thus it was treated as a (0) and not grouped.
Project Lead The Way, Inc.
Copyright 2009

43. NAND-NAND & NOR-NOR Networks
DeMorgan’s Law:
(a + b)’ = a’ b’ (a b)’ = a’ + b’
a + b = (a’ b’)’ (a b) = (a’ + b’)’
push bubbles or introduce in pairs or remove pairs.

44. NAND-NAND & NOR-NOR Networks

45. NAND-NAND Networks
Mapping from AND/OR to NAND/NAND

46. NAND-NAND Networks

47. Implementations of Two-level Logic
Sum-of-products
AND gates to form product terms (minterms)
OR gate to form sum
Product-of-sums
OR gates to form sum terms (maxterms)
AND gates to form product

48. Two-level Logic using NAND Gates
Replace minterm AND gates with NAND gates
Place compensating inversion at inputs of OR gate

49. Two-level Logic using NAND Gates (cont’d)
OR gate with inverted inputs is a NAND gate
de Morgan's: A' + B' = (A • B)'
Two-level NAND-NAND network
Inverted inputs are not counted
In a typical circuit, inversion is done once and signal distributed

50. Two-level Logic using NAND Gates (cont’d)

51. Conversion Between Forms
Convert from networks of ANDs and ORs to networks of NANDs and NORs
Introduce appropriate inversions ("bubbles")
Each introduced "bubble" must be matched by a corresponding "bubble"
Conservation of inversions
Do not alter logic function
Example: AND/OR to NAND/NAND A B C D Z
NAND

52. Conversion Between Forms (cont’d)
Example: verify equivalence of two forms A B C D Z A B C D Z
NAND
Z = [ (A • B)' • (C • D)' ]'
= [ (A' + B') • (C' + D') ]'
= [ (A' + B')' + (C' + D')' ]
= (A • B) + (C • D) ü

53. Conversion to NAND Gates
Start with SOP (Sum of Products)
circle 1s in K-maps
Find network of OR and AND gates

54. Multi-level Logic
x = A D F + A E F + B D F + B E F + C D F + C E F + G
Reduced sum-of-products form – already simplified
6 x 3-input AND gates + 1 x 7-input OR gate (may not exist!)
25 wires (19 literals plus 6 internal wires)
x = (A + B + C) (D + E) F + G
Factored form – not written as two-level S-o-P
1 x 3-input OR gate, 2 x 2-input OR gates, 1 x 3-input AND gate
10 wires (7 literals plus 3 internal wires) A
B C
D E F G X

55. Conversion of Multi-level Logic to NAND Gates
F = A (B + C D) + B C'
Level 1 Level 2 Level 3 Level 4
original
AND-OR network A C D B C’ F
introduction and
conservation of bubbles
redrawn in terms
of conventional
NAND gates B’

56. Conversion Between Forms
Example A X B C D F
(a)
Original circuit A X B C D F
(b)
Add double bubbles at inputs A D’ A X’ B C F
(c)
Distribute bubbles
some mismatches X
(d) B F C X’ D’
Insert inverters to fix mismatches

57. Making NAND circuits (Ex)
The easiest way to make a NAND circuit is to start with a regular, primitive gate-based diagram.
Two-level circuits are trivial to convert, so here is a slightly more complex random example.

58. Converting to a NAND
Step 1: Convert all AND gates to NAND gates and convert all OR gates to NAND gates.
AND
AND OR
AND
AND OR

60. Logic Circuit Analysis
Determining the behavior of a system given its description.
The description of the system is often provided
in the form of a circuit diagram.

61. Circuit Analysis Summary
After finding the circuit inputs and outputs, you can come up with either an expression or a truth table to describe what the circuit does
You can easily convert between expressions and truth tables
The analysis and synthesis tools presented are sometimes based on the fundamental concepts of Boolean algebra
Find the circuit’s
inputs and outputs
Find a Boolean
expression
for the circuit
Find a truth table

62. Digital Design Overview
Design digital circuit from specification
Digital inputs and outputs known
Need to determine logic that can transform data
Start in truth table form
Create K-map for each output based on function of inputs
Determine minimized sum-of-product representation
Draw circuit diagram
credential:
bring a computer
die photo
wafer :
This can be an hidden slide. I just want to use this to do my own planning.
I have rearranged Culler’s lecture slides slightly and add more slides. This covers everything he covers in his first lecture (and more) but may
We will save the fun part, “ Levels of Organization,” at the end (so student can stay awake): I will show the internal stricture of the SS10/20.
Notes to Patterson: You may want to edit the slides in your section or add extra slides to taylor your needs.

63. Design Procedure (Mano)
Design a circuit from a specification.
Determine number of required inputs and outputs.
Derive truth table
Obtain simplified Boolean functions
Draw logic diagram and verify correctness A 1 B C R S
S = A + B + C
R = ABC

64. Analysis versus Design
Design of a circuit starts with specification and ends up with a logic diagram.
Analysis for a combinational circuit consists of determining the function that the circuit implements with:
A set of Boolean functions or
A truth table, together with a possible explanation of the operation of the circuit.
We can perform the analysis by manually finding the Boolean equations or truth table.
The first step in the analysis is to make sure that the given circuit is combinational and not sequential (i.e. no feedback or storage elements).
School of Engineering

66. 1 1 +1 +1 2 10 Half Adder Add two binary numbers 0 0 0 0 0 1 1 0
A0 , B0 -> single bit inputs
S0 -> single bit sum
C1 -> carry out C A B S 1
Dec Binary
1 1
+1 +1
2 10

67. Multiple-bit Addition
Consider single-bit adder for each bit position.
A3 A2 A1 A0 A
B3 B2 B1 B0 B Ai
+Bi Ci Si
Ci+1 A B 1
Each bit position creates a sum and carry

68. Half-adder Full Adder Full adder made of several half adders
Si = Ci (Ai Bi)
Ci+1 = AiBi + Ci(Ai Bi)
Half-adder

69. A full adder can be made from two half adders (plus an OR gate).
Hardware repetition simplifies hardware design
A full adder can be made from
two half adders (plus an OR gate).

70. Putting it all together
Full Adder
Putting it all together
Single-bit full adder
Common piece of computer hardware
Block Diagram

71. 4-Bit Adder
Chain single-bit adders together.
What does this do to delay? C A B S

72. Negative Numbers – 2’s Complement.
Subtracting a number is the same as:
Perform 2’s complement
Perform addition
If we can augment adder with 2’s complement hardware?
110 = 0116 =
-110 = FF16 =
12810 = 8016 =
= 8016 =

73. +1 4-bit Subtractor: E = 1 Add A to B’ (one’s complement) plus 1
That is, add A to two’s complement of B
D = A - B

74. Adder- Subtractor Circuit

76. Designing Comparators Functionally

77. The comparison of two numbers Design Approaches
Magnitude Comparator
The comparison of two numbers
outputs: A>B, A=B, A<B
Design Approaches
the truth table
22n entries - too cumbersome for large n
use inherent regularity of the problem
reduce design efforts
reduce human errors
A < B
A[3..0]
Magnitude
Compare
A = B
B[3..0]
A > B

78. Magnitude Comparator
How can we find A > B?
How many rows would a truth table have?
28 = 256

79. Therefore, one term in the logic equation for A > B is A3 . B3’
Magnitude Comparator
Find A > B
Because A3 > B3
i.e. A3 . B3’ = 1
If A =1001 and
B = 0111
is A > B?
Why?
To determine whether A is greater or less than B, we inspect the relative magnitude of pairs of significant digits, starting from the most significant position. If the two digits of a pair are equal, we compare the next lower significant pair of digits, The comparison continues until a pair. of unequal digits is reached. If the corresponding digit of A is I and that of B is 0, we conclude that A > B. If the corresponding digit of A is 0 and that of B is 1, we have A < 3. The sequential comparison can be expressed logically by the two Boolean functions
Therefore, one term in the
logic equation for A > B is
A3 . B3’

80. Magnitude Comparator
If A = 1010 and
B = 1001
is A > B?
Why?
Because A3 = B3 and
A2 = B2 and
A1 > B1
i.e. C3 = 1 and C2 = 1 and
A1 . B1’ = 1
Therefore, the next term in the
logic equation for A > B is
C3 . C2 . A1 . B1’
A > B = A3 . B3’
+ C3 . A2 . B2’
+ …..

81. More difficult to test less than/greater than
Magnitude Comparison
Algorithm -> logic
A = A3A2A1A0 ; B = B3B2B1B0
A=B if A3=B3, A2=B2, A1=B1and A1=B1
Test each bit:
equality: xi= AiBi+Ai'Bi'
(A=B) = x3x2x1x0
More difficult to test less than/greater than
(A>B) = A3B3'+x3A2B2'+x3x2A1B1'+x3x2x1 A0B0'
(A<B) = A3'B3+x3A2'B2+x3x2A1'B1+x3x2x1 A0'B0
Start comparisons from high-order bits
Implementation
xi = (AiBi'+Ai'Bi)’

83. Multiplexers A multiplexer has
N control inputs
2N data inputs
1 output
A multiplexer routes (or connects) the selected data input to the output.
The value of the control inputs determines the data input that is selected.

84. 4– to– 1- Line Multiplexer

85. Quadruple 2–to–1-Line Multiplexer
Notice enable bit
Notice select bit
4 bit inputs

87. Black box with n input lines and 2n output lines
Binary Decoder
Black box with n input lines and 2n output lines
Only one output is a 1 for any given input
Convert binary information from n input lines to 2n output lines.
Known as n-to-m-line decoder (m = 2n).
May be used to generate the 2n minterms of n input variables.
Binary
Decoder n
inputs
m=2n outputs

88. 2-to-4 Binary Decoder Truth Table: F0 = X'Y' F1 = X'Y F2 = XY' F3 = XY
From truth table, circuit for 2x4 decoder is:
Note: Each output is a 2-variable minterm (X'Y', X'Y, XY' or XY) F0 F1 F2 F3 X
2-to-4
Decoder Y

89. 3-to-8 Binary Decoder Truth Table: F1 = x'y'z x z y F0 = x'y'z'

91. The simplest encoder is a 2n-to-n binary encoder
Encoders
If the decoder's output code has fewer bits than the input code, the device is usually called an encoder.
e.g. 2n-to-n
The simplest encoder is a 2n-to-n binary encoder
One of 2n inputs = 1
Output is an n-bit binary number . 2n
inputs n
outputs
Binary
encoder
An encoder is a digital circuit that performs the inverse operation of a decoder. An encoder has 2^n (or fewer) input lines and n output lines. The output lines, as an aggregate, generate the binary code corresponding to the input value, An example of an encoder is the octal-to-binary encoder

92. 8-to-3 Encoder Description: 23 = 8 inputs, 3 outputs
one input =1, others = 0’s
Each input generate unique binary code
8-to-3
Encoder D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2

93. 8-to-3 Encoder (truth table)
inputs
outputs D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 1
8-to-3
Encoder D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2

94. 8-to-3 Encoder (truth table)
inputs
outputs D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 1
8-to-3
Encoder 1 D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2

95. 8-to-3 Encoder (truth table)
inputs
outputs D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 1
8-to-3
Encoder 1 D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 1

96. 8-to-3 Encoder (truth table)
inputs
outputs D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 1
8-to-3
Encoder 1 D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 1

97. 8-to-3 Encoder (truth table)
inputs
outputs D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 1
8-to-3
Encoder 1 D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2 1

98. 8-to-3 Encoder (equations)
inputs
outputs D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 1
8-to-3
Encoder D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2
Output equations:
A0 = ?
A1 = ?
A2 = ?
Note: This truth table is not complete! Why?

99. 8-to-3 Encoder (equations)
inputs
outputs D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 1
8-to-3
Encoder D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2
Output equations:
A0 = D1 + D3 + D5 + D7
A1 = ?
A2 = ?

100. 8-to-3 Encoder (equations)
inputs
outputs D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 1
8-to-3
Encoder D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2
Output equations:
A0 = D1 + D3 + D5 + D7
A1 = D2 + D3 + D6 + D7
A2 = ?

101. 8-to-3 Encoder (equations)
inputs
outputs D7 D6 D5 D4 D3 D2 D1 D0 A2 A1 A0 1
8-to-3
Encoder D0 D1 D2 D3 D4 D5 D6 D7 A0 A1 A2
Output equations:
A0 = D1 + D3 + D5 + D7
A1 = D2 + D3 + D6 + D7
A2 = D4 + D5 + D6 + D7

102. 8-to-3 Encoder (circuit)A0 A1 A2 A0 A1 A2 D2 D3 D6 D7 D4 D5 D6 D7
Output equations:
A0 = D1 + D3 + D5 + D7
A1 = D2 + D3 + D6 + D7
A2 = D4 + D5 + D6 + D7

104. Performs the inverse of the operation of a MUX
DeMultiplexer
Performs the inverse of the operation of a MUX
It has one input line, the input from which is transmitted to one of 2n output lines
The output lines are selected based on the select inputs
1x2 DeMUX
D0 D1 E S

105. 1x4 DeMUX The circuit has an input E, the outputs are given by:
D0 D1 D2 D3
1x4 DeMUX E
S0 S1
The circuit has an input E, the outputs are given by:
D0 = E, if S0S1=00 D0 = S1’S0’ E
D1 = E, if S0S1=01 D1 = S1’S0 E
D2 = E, if S0S1=10 D2 = S1S0’ E
D3 = E, if S0S1=11 D3 = S1S0 E