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Charge Pump PLL

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**Outline Charge Pump PLL Loop Filter Design Loop Calibration**

Loop Component Modeling Loop Filter and Transfer Function Loop Filter Design Loop Calibration

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Charge Pump PLL The charge pump PLL is one of the most popular PLL structures since 1980s Featured with a digital phase detector and a charge pump Advantages Fast lock and tracking No false lock Phase Detector Charge Pump Loop Filter VCO N-Divider fi fo

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**C. Hogge, “A Self-correcting clock recovery circuit”, Dec, 1985**

Phase Detector Gives the phase difference between the input clock signal and VCO output signal Different types Nonlinear (such as Bang-Bang) Linear (such as Hogge’s Phase Detector) Linear PD output a digital signal whose duty ratio is proportional to the phase difference In Hogge’s PD, if the phase difference is θe , the output digital signal duty ratio is C. Hogge, “A Self-correcting clock recovery circuit”, Dec, 1985

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**Typical Phase Detector and Waveform**

Circuit Structure Output Waveform When locked Y. Tang, et., al., "Phase detector for PLL-based high-speed data recovery," Nov. 2002

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Charge Pump Convert a digital signal into current UP Iup Idn DN

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**Loop Filter Low pass filter 1st order**

2nd order (higher roll-off speed at high frequency) 3rd order & higher Ip Ip VC VC C1 C1 C2 R R

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**VCO Tuning gain KVCO is the most important parameter**

Usually coarse tuning and fine tuning

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**CP PLL loop modeling fi fo Phase Detector Charge Pump Loop Filter VCO**

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**2nd Loop Transfer Function**

Using a 1st order LPF: Active PI type Open-loop transfer function Closed-loop transfer function

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**3rd Loop Transfer Function**

Using a 2nd order LPF Let m=C2/C1 Open-loop transfer function Closed-loop transfer function

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Comparison When m becomes 0, the 3rd order loop degenerates into 2nd order loop 3rd order loop gives an extra high frequency pole, which increases the high frequency roll-off in jitter transfer 3rd order loop is widely used and can be treated as 2nd order loop for simplification Unfortunately, the 3rd order loop shows different jitter transfer from the 2nd order loop We focus on 3rd order loop

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**Simplification of 3rd Order Loop**

Define natural frequency ωn & damping ratio ξ Then totally 3 loop parameters: ωn, ξ &m Simplified transfer function

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**LPF Design Consideration**

3-dB frequency – easy to control Roll-off speed– easy to meet with 2nd and 3rd order transfer function Jitter transfer (jitter peaking)

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**Jitter peaking of 2nd order loop**

Jitter peaking can be reduced or eliminated by increasing the damping ratio Eliminated when damping ratio ξ >1 Large damping ratio leads to slow closed-loop response Usually suggested ξ=5 to meet the jitter peaking spec

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**Jitter peaking of 3rd order loop**

Usually believed to be similar as the 2nd order loop Actually quite different from the 2nd order loop case Jitter peaking always exists even with very large ξ Need to be treated carefully

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**Jitter peaking is dependent on ξ and m**

m=0 (2nd loop) jitter peaking can be reduced or eliminated by using large ξ m>0 (3rd loop) ξ is quite small, increasing ξ will decrease the jitter peaking; ξ is larger than a threshold value ξm, increasing ξ will increase the jitter peaking Jitter peaking versus damping ratio and capacitance ratio

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**How to achieve the minimum jitter peaking**

For given m, there exists the minimum jitter peaking --the minimum jitter peaking can be viewed as a function of m: JP(m) The minimum jitter peaking under a given m is achieved only by using a proper ξ --ξ should be a function of m: ξm(m) JP(m) ξm(m)

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**Sampling effect of phase detector**

The phase detector has sampling effect, especially when its rate is not much higher than the loop cut-off frequency Approximate TF of phase detector :

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**Jitter Peaking w/ PD Sampling Effect**

It causes the jitter peaking worse when ξ is very small, jitter peaking decreases when ξ increases; when ξ becomes larger than ξm, jitter peaking increases with ξ; when ξ is larger than ξm2, jitter peaking decreases when ξ is increased further

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**JP(m) and ξm(m) with sampling effect**

JP(m) with sampling effect ξm(m) with sampling effect

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**Tables of JP(m) and ξm(m) for practical design**

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**Design procedures of charge pump PLLs for jitter transfer characteristic optimization**

Decide the maximum tolerated jitter peaking and find capacitance ratio m using JP(m). Use ξm(m) to find the optimal damping ratio value ξm; Decide ωn according to the application, choose reasonable KVCO, and calculate Ip, R, C1 and C2; Use time domain simulation to verify that the expected jitter transfer performance can be achieved

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Design example Target: to design a 2.5GHz CP PLL, meet the jitter specification Design parameters: m=0.005 and ξ=5.0 Simulation result: jitter peaking is only 0.078dB Jitter transfer characteristic of the designed PLL

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**More Discussion on Loop Transfer Function**

The above discussion suggests to use very small m to meet the jitter peaking However, if m is too small, the effect of the second capacitor can even be ignored Compromise should be made between jitter peaking and other performance

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**Charge pump PLL calibration**

Purpose: make the loop transfer characteristic meet the spec Calibration types: Component calibration Loop calibration

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**Charge Pump Calibration**

Purpose: minimize the mismatching between UP and DOWN current Method: switch small current sources UP UP Iup Iup ICAL ICAL … ICAL ICAL Idn Idn DN DN

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**Charge Pump Calibration Procedure**

Use the UP or Down current to charge/discharge a capacitor Compare the time difference and calculate the calibration code Ref CLK UP Vref Counter Iup R/S Comparator Idn DN

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**VCO Coarse Tuning Purpose: to speed frequency tracking**

Method: make use of the coarse tuning functionality of the VCO When extreme high frequency range is desired, double VCOs can be used to help achieve fine frequency tuning resolution

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**VCO Coarse Tuning Procedure**

Apply different coarse tuning voltage (output from a low resolution coarse tuning DAC) Measure VCO output frequency respectively Compare to the reference frequency Write the desired DAC code into register

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**Time Constant Calibration**

Purpose: calibrate the loop transfer function time constant so that the 3-dB frequency meets the spec Method: switch small CAL capacitors CCAL CCAL … CCAL CCAL

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**Time Constant Calibration Procedure**

Ref CLK Vref Counter Vref Vx R C Comparator

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Loop Gain Calibration Purpose: calibrate the loop transfer gain to the desired value Method: switch different charge pump output current (KVCO is not changeable usually)

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